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ep2c35_3.8_full_add
- 这个程序用verilog硬件语言编写。用来在FPGA内实现全加器。并且可以将输出显示在外部LED灯上等。-this program is writen by verilog HDL.it is the full adder for FPGA.users can read the result from the LEDs.
quanjiaqiheDchufaqi
- 设计一个全加器元件，再用该元件连成4位二进制加法器 设计一个D触发器元件，再用该元件连成4位寄存器 -Design a full adder component, then the component with a 4-bit binary adder design a D flip-flop element, then the components together into four registers
four
- 大学VHDL实验科目报告四位全加器设计报告-University of VHDL test subjects reported four full adder design report
full_adder-and-half_adder
- 在Quartus II中用VHDL语言编写的全加器与半加器程序，全加器是调用半加器来实现的。-In the Quartus II VHDL language using the full adder and half adder program, full-adder is called a half adder to achieve.
FPGAadder
- 现场可编程门阵列（FPGA）是目前应用非常广泛的一种专用集成电路。在FPGA平台上实现了2位全加器硬宏的设计-Field programmable gate array (FPGA) is widely used as a specific integrated circuit. The FPGA platform for a two full adder hard macro design
mult
- 4级流水乘法器，本文利用FPGA完成了基于半加器、全加器、进位保留加法器的4比特流水乘法器的设计，编写VHDL程序完成了乘法器的功能设计，并通过Modelsim进行了仿真验证。-Four water multipliers, this paper complete FPGA-based half adder, full adder, carry-save adder 4 bit pipeline multiplier design, write VHDL program to complete
full_add
- 全加器，可移植性很强，只需要变换一下里面的数字就能得到任意的全加器！-The counter, portability is very strong, only need to a change in the inside of the digital can get any counter!!!!!
BCD_add
- BCD全加器，用QuartuesII 开发的源码，包括工程文件，下载就能用的，在DE2-70上直接使用。-BCD full adder, with QuartuesII source development, including the project file, download will be able to use in directly on the DE2-70.
1_02_FullAdd4
- 四位元全加器,為Verilog/VHDL構成的IP模組電路-4bit fulladder
AdderE-modelSim
- 全加器ModelSim工程，modelsim的仿真模型，在quartus下可运行-Full adder ModelSim project, modelsim simulation model can be run under the quartus
adder
- 用VHDL语言编写的全加器文件 希望对大家有所帮助 原创空间 大家多多支持-failed to translate
addr4
- 可以实现四位全加器，使用四个全加器串联的方式，不是快速进位位的方式-Can achieve four full adder, full adder using four series were not as fast carry bit of the way
ADDER
- verilog DHL编写的一位全加器，编译通过。稍作修改便可编程任意位加法器。-verilog DHL write a full adder, compiled by. Slight modifications can be programmed any adder.
Verilog
- 基于verilog HDL编写的各种实例。。里面记载了计数器，全加器，等等的代码。-Based on various examples written in verilog HDL. . Recording the counter, full adder, and so the code.
09081113
- 简单计数器，分频器，全加器等vhdl程序等-Simple counter, divider, adder vhdl procedures such as
four_bit-full-adder
- 四位的全加器，包含8421码与2421码的相互转换，2421码的加法修正-Four of the full adder, including 8421 yards and 2421 yards of the conversion, the addition of amendments to 2421 yards
f_adder_8
- 利用vhdl编写的8位全加器程序，适合初学者了解并掌握VHDL编写规则。-Using vhdl write 8-bit full adder of the program, suitable for beginners to understand and master the VHDL written rules.
verilog
- Verilog初学者例程:1位全加器行为级设计、1位全加器门级设计、4位超前进位加法器、8位bcd十进制加法器、8位逐次进位加法器、16位超前进位加法器、16位级联加法器、多路四选一门级设计、七段译码器门级设计-Verilog routines for beginners: a behavioral-level design full adder, a full adder gate-level design, 4-ahead adder, decimal 8-bit bcd adder, 8-
8f_adder
- 8位全加器 实现8位全加器，先半加器 后一位全加器，最后8位全加器-eight add eight add eight add eight add eight add
dd
- 八位全加器的源代码，用verilog编写，没有附带测试程序-eight summury