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cpu
- 用全加器设计8位运算器逻辑电路图 2、根据逻辑电路用 VHDL编程实现 3、调试编译通过后，仿真 -this file can help you learn the design of cpu
EDA
- 课程实验，VHDL语言实现半加器全加器，频率计等，共四个-eda
for_ws
- 裡頭有加法器,全加器,rippple adder-full adder ,rippple adder
Adder4
- 源码，内容是用VHDL语言编写的四位全加器-Source code, using VHDL language of the four full-adder
Full_adder
- 全加器的VHDL逻辑编程，外加两个全功能，这个过程有些简单，但可能有一些初学者的帮助。-Full adder VHDL logic programming, plus two full-function, this process some simple, but there may be some beginners help.
ex1.v
- 用Verilog HDL 实现的4位二进制全加器。-4-bit full adder implemented with Verilog HDL
experiment1
- VHDL实验一，利用原理图输入法设计4位全加器-VHDL test 1, use of schematic input 4-bit full adder design
full_aller
- 这是基于VHDL的一位全加器设计的程序，分析过程全面-This is based on a full adder VHDL design process, a comprehensive analysis process
FullAdder
- 设计全加器电路 有需要的同学可以下载来-Full adder circuit design students need to see is available for download
f_adder
- 1位全加器，原理图设计，包括波形仿真，和打包，可以直接在Quartus6..0中直接使用-A full adder, schematic design, including the waveform simulation
sy1_yt
- 在max-plus 环境下使用vhdl语言实现用半加器组成全加器的功能。-In the max-plus environment, using vhdl language component with half adder full adder function.
ALU
- 算术逻辑部件的verilog代码，它能够实现半加器、全加器、比较、按位与、按位或、按位异或、加一、减一的操作-Arithmetic logic unit of the verilog code, it can achieve half adder, full adder, compare, bitwise and, bitwise or, bitwise xor, plus one, minus one operation
fadd16
- 实验用16位全加器的VHDL代码，适合初学者学习，数电学习的好工具。 -Experiment with 16-bit full adder VHDL code for beginners to learn, a good tool to learn a few power.
Verilog
- 各类verilog源代码 计数器，全加器，串行快等。-All verilog source code counter, adder, serial quick.
fulladde
- 全加器源代码，VHDL语言编写，有需要的参考参考-Full adder source code, VHDL language, the need to reference information
FPGA1
- 4位全加器 仿真波形一点问题都没有 我调试过-ADD
adder
- 完成8位全加器功能，从最底层的半加器到1位全加器在到8位全加器的完整设计-adder
ex15
- 四位全加器的集成版图设计，基于tanner软件平台的layout设计，欢迎下载-The integration of four full adder layout, tanner software platform based on layout design, please download
cadence_multi-threshold
- linux下(fedora版本)的cadence中编译4位全加器的实现, 在不同的阈值电压调解下观察点路的总体power和速度,以及逻辑的正确性. 可能会用到NCSU的FREEPDF工具包-this is a package of three projects, low-vth, high-vth, and optimum architecture vth four bit full adder design. In the environment of Cadence and then sim
qj
- 全加器。使用Vhdl语言实现数字电路全加器功能，算法比较简单，供初学者参考。-Full adder. Digital circuits using Vhdl language full adder function, the algorithm is relatively simple for advanced users.