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6_VHDL-application-design
- VDHL应用实例，包括组合逻辑电路设计，时序逻辑电路设计，存储器设计，状态机设计 -VDHL application design samples, including combined logic design, timing logic design, memory design, and status machine design
ckkz-delay
- 一个单片机C语言状态机接收串口指令并控制步进电机的程序-A single-chip C-state machine receives serial command and control the stepper motor program
SJ_FSM
- 这是有限状态机的学习资料，详细介绍了设计有限状态机的步骤和方法，对想学习数字系统设计的朋友应该有所帮助-This is a finite state machine learning materials, details the steps to design finite state machines and methods for studying digital system design to a friend should help
three_machine_study
- verilog 三段式状态机的写法，很好的Pdf-verilog three-state machine is written, a good Pdf
4x4keyscan
- 4x4按键扫描程序 是基于状态机的有按键消抖按键扫描程序-4x4 key scanner is based on the state machine has buttons debounce key scanner
20110414
- 状态机的使用范例。可以自行添加所需要的功能。-The use of state machine example. Can add the required functionality.
VHDL
- VHDL程序(含任意波发生器，一些芯片的驱动，以及状态机的典型设计等)-VHDL program (including arbitrary waveform generators, a number of chip drivers, and a typical state machine design, etc.)
1
- 关于AD采样，用的是ADC0809，运用状态机编程-About AD sampling, using a ADC0809, the use of state machine programming
VerilogDesignand-test_PdfPCode
- Verilog 设计与验证源码+PDF，经典教程，对与RTL和状态机的理解有很大帮助，适合FPGA开发工程师。-Verilog design and verification source+ PDF, classic tutorial, and state machine understanding of RTL helps a lot, suitable for the FPGA development engineers.
fms
- 这是个有关有限状态机编程的资料，希望对你有帮助-FMS, which is the state machine information, want to help you! ! !
cifa-vcPP
- 一款编译原理中的词法分析器，利用有限状态机的机制，能够解析C语言代码的词法结构，将每一个句子变成一个一个单词的形式。-A lexical analyzer in the compiler theory, finite state machine mechanism, able to resolve the lexical structure of C language code, each a one-word sentence into a form.
state-machine-design
- Verilog and VHDL状态机设计，内含源代码，希望对大家有所帮助。-Verilog and VHDL state machine design, including source code, we want to help.
fsm
- rfid 电子标签设计数字基带处理状态机设计-rfid electronic card digital signal processing of fsm
Integrator-comb_timing-state
- 积分梳状滤波器和时序状态机的Verilog语言描述，适合硬件描述初学者-Integrator-comb filter and timing the Verilog language to describe state machines, hardware descr iption suitable for beginners
canopen-spec
- CANopen协议的详细说明，清楚的解释了什么是对象字典，以及SDO，PDO的通信规范，对CANOPEN通信状态机也作了说明。-CANopen protocol details, a clear explanation of what is an object dictionary, and SDO, PDO' s communications standards, for CANOPEN communication state machine are also described.
Interactive-state-machine
- 交互状态机建模，交互状态机能够使用通过公共寄存器通信的独立的a l w a y s语句进行描述。 示的两个交互进程的状态图， T X是一个发送器， M P是一个微处理器。如果进程T X不忙，进 程M P将要发送的数据放置在数据总线上，然后向进程T X发送信号L o a d T X，通知其装载数据 并开始发送数据。进程T X在数据传送期间设置T X B u s y表明其处于忙状态，不能从进程M P接 收任何进一步的数据。-Interactive state machine mode
trafficlightsa
- 东南大学 短学期数字系统设计中的 交通灯设计 通过状态机实现-Southeast University in the short-term digital system design through the traffic light state machine design
mytftp
- 利用状态机写的一个mytftp跟ftp功能一样-Written using a state machine with the ftp functions as mytftp
MYCRC
- 由于altera公司的CRC生成和校验模块不支持本系统使用的Cyclone IV E系列FPGA，因此本文独立设计了CRC模块。该模块的接口与altera公司的CRC模块接口基本一致，能够对16位输入的数据流进行CRC校验码生成和校验。本文采用CRC-CCITT生成项，其表达式为：X16+X12+X5+X0。本模块需要startp信号及endp信号指示数据传输的起始及结束。本模块采用状态机设计，对于数据头和数据尾分别由不同的状态来处理。在本模块中，使用了for循环，这会消耗较多的FPGA资源，但
FSM_Mealy
- Mealy型有限状态机设计，设计软件quartus，有详细注释-Mealy type finite state machine design, design software, quartus, with detailed notes