搜索资源列表
tft35inch_2C8_test
- 基于FPGA的ip核lcd控制器 320240分辨率-ip nuclear lcd controller FPGA-based resolution of 320,240
8pic_MCU
- 8位MCUIP核的设计与应用（verilog IP核设计）PIC处理器 西安电子科技大学硬件工程师培训资料-Design and Application of 8 MCU IP cores (verilog IP core design) PIC processor Xi an University of Electronic Science and Technology Hardware Engineer training materials
mcu51
- 基于IP核的51mcuFPGA程序，有顶层文件图，可以直接运行，有助于对mcu的工作原理和FPGA的理解-IP core based on the 51mcuFPGA program, there are top-level file map, can be directly run, contribute to the working principle of the MCU and FPGA understanding
SEG7_IF
- SEG7_IP.v是七段数码管的驱动程序，符合avalon总线协议，可以直接添加七段数码管的ip核使用。-SEG7_IP.v is the seven segment digital tube driver, in line with the Avalon bus protocol, you can directly add the seven segment digital tube IP nuclear use.
ReadFifo
- QuartusII 15.0版本中，在Qsys中建立的自己定制的符合Avalon总线协议的IP核，实现功能将输入的TS流识别并存储到FIFO中，Nios核再通过总线对数据进行读取-QuartusII 15 version of the Qsys in to establish their own custom Avalon bus protocol in line with the IP core, the realization of the function to enter the TS
FIFO_TEST
- XILINX FIFO IP核测试程序，已经通过测试，方便可用-XILINX FIFO IPcore testbench
fft_core_test
- 基于FPGA的FFT的IP核实现，有其详细源码，采用verilog语言编写，内容详细-The FFT based on FPGA IP core implementation, has its source in detail, using verilog language writing, detailed content
SOPCIINIOSII-guiding-book
- SOPCIINIOSII实验指导书（第二版）和 实验操作手册，以ALTERA公司的NIOSII IP核为中心，详尽的说明NIOSII的SOPC设计，适用于SOPC-NIOSII EDA/SOPC实验开发平台的系列产品-SOPCIINIOSII experimental guide book (second edition) and the experimental operation manual to ALTERA company NIOSII IP core-centric, detaile
axi_spi_ds742
- xilinx，microblaze的spi ip核的datasheet。xilinx官网速度慢，分享给有需要的朋友。 -xilinx, microblaze the spi ip core datasheet. xilinx Officer slow speed of network share to a friend in need.
myavalonvideo
- 自动聚焦视频采集评价计算IP核，TVP5150接口，sobel计算，均值滤波等。可直接添加到SOPC或Qsys中。-Auto focus video capture uation calculation IP core, TVP5150 interface, Sobel calculation, mean filter, etc.. Can be added directly to SOPC or Qsys.
pwm
- 通过该IP核输出三路pwm波，可用来控制一个舵机和两块L298N驱动板，从而控制电机。-IP core output by the three-way pwm wave can be used to control a servo drive plate and two L298N to control the motor.
spi_ip
- SPI总线的IP核，可以实现半双工spi通信-SPI bus IP core, can achieve half-duplex communication spi
Verilog-IIC-read-MPU6050-Filter
- 本代码实现了读MPU6050 三轴6个数据，用其中的GY和AZ、AX结合融合滤波算法，解出X单轴角度，并在黑金开发板的EP4C15F17C8芯片上调试成功，±5°范围内LED灯灭，左右摆动时相应左右灯亮。 顶层模块每隔5ms，发出一个is_read高电平，下面的模块读取一次数据，并计算，更新LED状态。有关计算都用的ip核，占用资源很大。希望对小小小小白有所帮助。 -Verilog codes read 6 axis data of MPU6050, and use GY AZ AX w
PCIe
- 使用Altera PCIe IP核,补充PCIe事物层，完成了PCIe设备端硬件设计。Windows和Linux下，安装合适驱动后，可读写PCIe设备。-Use Altera PCIe IP core, supplement PCIe transaction layer, complete PCIe device side hardware design
xilinx_pcie_dma_driver
- xilinx官方给的PCI Express DMA IP核的Linux下的驱动代码，以及代码文档-PCI Express DMA IP core of Linux driver code official to under xilinx, and code documentation
viterbi_soft
- 维特比译码器，调用IP核，软判决输入，开发平台Xilinx Spartan-6系列FPGA-viterbi decoder, using IP core resource, soft decision input,develop platform is Xilinx Spartan-6 series FPGA
15_IP_core
- ata, 3des vgs等ip核。 ECE395 GPU: -ata, 3des vgs and other ip core. ECE395 GPU:
colorbar
- VGA在800*600分辨率屏上显示竖型彩条10份，扫描时钟是通过例化IP核PLL_CLK进行分频得到40MHz-VGA color display type vertical strip 10 parts, scan clock by instantiating the IP core PLL_CLK performed on 800* 600 resolution screen frequency to be 40MHz
PCIE_14_Complete
- FPGA PCIE的IP核控制，可以用modelsim直接仿真，观察信号。-IP core for PCIE of FPGA,able to simulate with modelsim and check the signal
IIC
- FPGA I2C的IP核控制，可以用modelsim直接仿真，观察信号。-IP core for I2C of FPGA,able to simulate with modelsim and check the signal