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2345676588FPGAxiebofenxi
- 本文给出一种基于FPGA的新型谐波检测系统的设计方案。在该方案中,采用FPGA实现快速的FFT运算,采用数字锁相环来同步被测信号,以减小由非同步采样所产生的误差并给出实现的设计实现。数字锁相环和FFT算法用VHDL语言设计实现,该方案能提高谐波分析的精度以及响应速度,同时大大地精简了硬件电路, 系统升级非常方便。-This paper presents a new FPGA-based harmonic detection system design. In the scheme, using
PLL
- 此文件为PLL的测试文件,用VHDL语言编写。可供参考。-PLL TEST
pll
- 利用qaurtus的内的ip核定制锁相环实现对信号的倍频-The use of the ip qaurtus approved system PLL multiplier on signal
PLL-C
- csl for pll programming
plldemo
- This an example of PLL demo-This is an example of PLL demo
PLL_50MHz_to_12MHz
- Verilog HDL语言编写EP2C8Q208芯片PLL分频的简单程序,50MHz分频为12MHz-Verilog HDL language,EP2C8Q208 chip, PLL frequency of simple procedures, 50MHz to 12MHz frequency
qpsk_PLL
- QPSK的锁相环程序,在MATLAB环境下编写的,用来进行QPSK通信系统的仿真和实际信号载波同步的提取-QPSK PLL program, written in the MATLAB environment, QPSK communication system used for simulation and the actual extraction of the signal carrier synchronization
ATMEL_PLL_Filter_CALCULATOR_AT91_2v91
- ATMEL PLL Filter CALCULATOR
sdram
- 通过 UART 读写 SDRAM verilog 源代码 通过 UART 的接口发送命令来读写 SDRAM 命令格式如下: 00 02 0011 1111 2222 00: 写数据 02: 写个数 0011: 写地址 1111 2222: 写数据, 是 16 bit, 每写完一个数据,向串口发送 FF 回应; 输出: FF FF 01 03 0044 01: 读sdram 03: 读的个数 0044: 读的地址 输出: xxxx xx
track
- gps信号的跟踪,采用锁相环实现,包括码环的跟踪和载波的跟踪环-gps signal tracking, the use of PLL implementation, including code and carrier tracking loop tracking loop
Matlabpll
- 基于Matlab的数字锁相环的仿真设计,一篇毕业论文,对数字和模拟锁相环进行了详细的分析和仿真-Matlab-based simulation of digital PLL design, a thesis on digital and analog phase-locked loop for a detailed analysis and simulation
dfefe.doc
- 该高频正弦信号发生器基于直接数字频率合成(DDS)和数字锁相环技术(DPLL),以微控制器(MCU)和现场可编程逻辑门阵列(FPGA)为核心,辅以必要的外围电路设计而成。系统主要由正弦信号发生、红外遥控、高速模数(A/D)-数模(D/A)转换、信号调制和后级处理等模块组成。-The high-frequency sinusoidal signal generator based on Direct Digital Synthesis (DDS) and digital PLL (DPLL), a
PLL_simple
- PLL simulator on MATLAB
verilog_PLL
- verilog 写的硬件 pll 锁相环实现-verilog to pll
PSIMbasedsimulationmodelofthedesignofPLLPLL
- 基于PSIM的锁相环_PLL_仿真模型设计PSIM-based simulation model of the design of PLL _PLL_-PSIM-based simulation model of the design of PLL _PLL_
Technologyofcarriertrackingforhighdynamicsignalsba
- 高动态给载波的跟踪带来了很大的困难,本文研究采用锁频环( FLL) 和锁相环( PLL) 相结合的方法来实现 载波跟踪-High dynamic to the carrier' s tracking has led to great difficulties, this paper uses frequency-locked loop (FLL) and phase-locked loop (PLL) methods to achieve a combination of carrie
AD-PLL
- 基于VHDL的全数字锁相环的设计与实现,quartusII的仿真程序。-DPLL based on VHDL Design and Implementation, quartusII the simulation program.
PLL-MB87006_HGG
- AVR Bascom Fujitsu pll control
8051withTSA5055_Pll_UV3
- TSA5055 PLL with any 8051 variant
pll
- 本文讲述锁相环的工作原理,锁相环路实际上是一个相差自动调节系统。-This article describes the working principle of PLL, PLL is actually a difference between the automatic adjustment system.