搜索资源列表
A-fast-lock-PLL-charge-pump-design
- 一种快速锁定电荷泵锁相环的设计，采用ADS进行仿真-A fast lock PLL charge pump design
PLL-STC(V3)
- 锁相环控制实例,可通过上位机或者其它监控系统控制,调节PL2313输出频率-PLL control instance, can be monitored by PC or other system control, adjust the output frequency PL2313
PLL
- 9s12锁相环配置程序，1.5倍频。编译环境Codewarrior4.6-9s12 PLL configuration program, 1.5 octave. Build environment Codewarrior4.6
test_sdram
- 对SDRAM进行读写，工程内部分为PLL以及复位处理模块、写SDRAM逻辑模块、读SDRAM逻辑模块、SDRAM读写封装模块、读写缓存FIFO模块、串口发生模块等。工程基于altera的Quartus II 10.1进行设计，使用更高版本的软件均可。-SDRAM read and write for the project is divided into the internal PLL and reset processing module, SDRAM write logic block,
PLL-phase-lock-loop-application
- 锁相环PLL原理与应用，锁相环PLL原理与应用-PLL phase lock loop principle and application
power_3phpll
- 这个示范ilustrates使用的三相Programmble电压源，PLL和可变频率正序电压和功率的测量块-This demonstration ilustrates use of the 3-Phase Programmble Voltage Source, PLL and Variable-Frequency Positive-Sequence Voltage and Power Measurement blocks
PLL
- The simulation file is the Phase lock loop with dq theory with unbalance input volatges
Ramesh3
- three phase harmonics p-three phase harmonics pll
PLL
- SOPC 系统集成编译的PLL IP核 Verilog代码-pll ip core in SOPC
pll
- 关于pll的simulink模型，希望对大家有用。-a module of pll by using simulink.hope it be helpful
adfmreceiver
- The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency,iωand the respective output frequency,oωvia p
PLL-Hardware-Design
- systemiew的功能示例，主要讲述在32位条件下有systemview进行PLL硬件设计和软件仿真的方法-PLL Hardware Design and Software Simulation Using the 32-bit of SystemView by ELANIX
PLL-Hardware-Design
- systemiew的功能示例，主要讲述在32位条件下有systemview进行PLL硬件设计和软件仿真的方法-PLL Hardware Design and Software Simulation Using the 32-bit of SystemView by ELANIX
my_uart1_VERILOG_using-PLL
- Verilog uart example, RS232的Verilog例子。PC 发送一个字节（byte）到板子（FPGA），板子回发一个(byte+1).例子简洁，有注释。用到PLL，而且有3：2次数据采用-Verilog uart example，Verilog RS232 example，it s easy to understand, PC send 1 Byte RS232 code to FPGA, FPGA return 1 tht code，but Byte+1， Using P
PLL
- 一篇关于PLL的文章，很经典，20多页，欢迎下载。-An article on the PLL, classic, 20 pages, please download.
PLL
- PLL锁相环的详细介绍，电子书包括设计及应用，对研究锁相环的很有用-Introduction of PLL，include design and application，it s useful for research of PLL
fpga-pll
- cyclone的pll应用，精确翻译，适合需要又不想看英文文献的同学。-cyclone the pll applications, accurate translation, suitable for students of English literature need not want to see. Undo edits Dictionary
Static-PLL
- 基于Actel开发平台的静态锁相环设计，verilog实现-Actel development platform based on the static PLL design, verilog realized
pll
- PLL的几个程序打包，关于锁相环的，具有一定参考价值-PLL-packaged, downloaded from the Internet, seek to help, is currently being studied
TIMEQUEST-PLL
- 在TIMEQUEST约束PLL输出方法 FPGA-PLL output method FPGA TIMEQUEST constraints