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quanjiaqiheDchufaqi
- 设计一个全加器元件，再用该元件连成4位二进制加法器 设计一个D触发器元件，再用该元件连成4位寄存器 -Design a full adder component, then the component with a 4-bit binary adder design a D flip-flop element, then the components together into four registers
four
- 大学VHDL实验科目报告四位全加器设计报告-University of VHDL test subjects reported four full adder design report
ADDER
- .采用原理图输入法和文本输入法实现全减器，分层设计，底层由半加器（也用原理图输入法）和逻辑门组成； 2.给出此项设计的仿真波形； 3.选择实验电路进行验证, 由发光管指示显示结果。 -. The use of schematic and text input method input method to achieve full subtracter, hierarchical design, the bottom of the half adder (also used schem
full_adder-and-half_adder
- 在Quartus II中用VHDL语言编写的全加器与半加器程序，全加器是调用半加器来实现的。-In the Quartus II VHDL language using the full adder and half adder program, full-adder is called a half adder to achieve.
FPGAadder
- 现场可编程门阵列（FPGA）是目前应用非常广泛的一种专用集成电路。在FPGA平台上实现了2位全加器硬宏的设计-Field programmable gate array (FPGA) is widely used as a specific integrated circuit. The FPGA platform for a two full adder hard macro design
big_caculator
- This Source is Full Adder Algorithm over 4bytes
BCD_add
- BCD全加器，用QuartuesII 开发的源码，包括工程文件，下载就能用的，在DE2-70上直接使用。-BCD full adder, with QuartuesII source development, including the project file, download will be able to use in directly on the DE2-70.
1_ADDER
- 实现加法功能,是半加法器，可扩充为全加法器。-Achieve additive function is half adder, full adder can be expanded to.
AdderE-modelSim
- 全加器ModelSim工程，modelsim的仿真模型，在quartus下可运行-Full adder ModelSim project, modelsim simulation model can be run under the quartus
ripple_carry_adder
- ripple carry adder instantiated by full adder
addr4
- 可以实现四位全加器，使用四个全加器串联的方式，不是快速进位位的方式-Can achieve four full adder, full adder using four series were not as fast carry bit of the way
Verilog
- 基于verilog HDL编写的各种实例。。里面记载了计数器，全加器，等等的代码。-Based on various examples written in verilog HDL. . Recording the counter, full adder, and so the code.
full_adder_44
- full adder 4x4 for spartan 3 fpga
f_adder_8
- 利用vhdl编写的8位全加器程序，适合初学者了解并掌握VHDL编写规则。-Using vhdl write 8-bit full adder of the program, suitable for beginners to understand and master the VHDL written rules.
Full_Adder
- four-bit Full Adder using gates design
verilog
- Verilog初学者例程:1位全加器行为级设计、1位全加器门级设计、4位超前进位加法器、8位bcd十进制加法器、8位逐次进位加法器、16位超前进位加法器、16位级联加法器、多路四选一门级设计、七段译码器门级设计-Verilog routines for beginners: a behavioral-level design full adder, a full adder gate-level design, 4-ahead adder, decimal 8-bit bcd adder, 8-
jiafaqi
- 数字系统设计及VHDL实践半加器与全加器源代码-half-adder and full-adder
ls139
- 全加器程序编写，用VHDL语言实现四位全加器的加法运算-Full adder programming, using VHDL language to achieve the addition of four full-adder operation
EDA
- EDA教程实用技术,基于VHDL的八位数字全加器-EDA tutorials and practical techniques, VHDL-based eight-digit full adder
fadder8
- 基于VHDL语言，编写一个32位全加器文件，可直接编译-Based on VHDL language, write a 32-bit full adder files can be directly compile