搜索资源列表
cordic_pipelined
- CORDIC算法的流水线verilog HDL实现，包含modelsim仿真所需的设计文件与testbench。-This is an implementation of CORDIC algorithm in verilog HDL, which contains design code and testbench.
bw_scoresource
- This the bowling score source code. Edit tool is xilinx corp ISE. I used the Modelsim for simulation.-This is the bowling score source code. Edit tool is xilinx corp ISE. I used the Modelsim for simulation.
fsk
- 简单的FSK程序，并且经过了ModelSim检验-FSK simple procedure, and after a ModelSim test
modelsim-run-one-step--Error-
- 用modesim仿真的时候会出现只运行了一步就不动了，显示"# ** Error: (vsim-3601) Iteration limit reached at time 0 ps."的解决方法。-With modesim simulation run only when there will be a step not move, display " #** Error: (vsim-3601) Iteration limit reached at time 0 ps." S
modelsim_image_processing
- 使用fpga开发图像处理时往往会遇到各种困难，调试周期比较长，尤其是输入输出接口。但我们想先研究算法，所以这里给出了一个工具，可以帮助我们实现这个功能。这个工具作为辅助工具，算法实现部分可以通过modelsim来完成-Image processing using fpga development often will encounter various difficulties, debug cycle is relatively long, especially input and outpu
dvi_output
- DVI output modelsim simulation
VLSI-Project-Median-filer
- FPGA和ASIC实现的图像中值滤波模块，各模块的仿真结果以及MATLAB,Modelsim联合仿真。这是中科大超大规模集成电路设计优化的final project。附有最终版的report和presention。-FPGA and ASIC implementation of image filtering modules, each module of the simulation results and MATLAB, Modelsim co-simulation. This is the
coa
- 在Modelsim中实现类MIPS多周期流水化处理器-In Modelsim achieve class multi-cycle pipelined processor MIPS
mseq
- 在fpga开发板上运行，生产m序列。 包括m1.v为主文件，mtest.v是测试文件，用于modelsim 仿真-In fpga development board to run the production m sequence. Including m1.v primary file, mtest.v is a test file for modelsim simulation
FPGA_trainning2013A
- 在EDA实验课上面，自己编写的NCO程序，可以产生出比较真实的正弦波、三角波以及锯齿波，用VHDL程序编写，有modelsim仿真textbench程序-On EDA experiment, oneself write the NCO program, can produce more real sine wave, triangular wave and sawtooth wave with VHDL programming, have the modelsim simulation text
filter
- 滤波器，经过modelsim仿真得到了正确的结果-Filter through modelsim simulation get the correct result
dingshi
- 定时器加数码管显示源码，以及test bench测试模块源码，经modelsim仿真结果正确-Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct
counter10
- verilog编写的10进制计数器，并且功能仿真正确。软件为quartus II 11.0,和Modelsim-verilog prepared 10 binary counter, and functional simulation is correct. Software quartus II 11.0, and Modelsim
rng
- wishbone规格下的rng代码的实现，自己编写顶层模块可以在modelsim下实现仿真-wishbone rng specifications under the implementation of the code, you can write your own top-level module under modelsim for simulation
LineBuffer
- Verilog HDL的移位寄存器的modelsim仿真
FPGA_ENVIRONMENT_BUILD
- FPGA环境的搭建，安装altera qaurtus ii 11.1和modelsim 6.5d se 图形化简单实用。-FPGA environment to build, install altera qaurtus ii 11.1 and modelsim 6.5d se graphically simple and practical.
video_stream_scaler_latest.tar
- 参数化的高清视频缩放源程序，配有文档说明。还有modelsim仿真源代码。-Parametric HD video scaling source, with documentation. There modelsim simulation source code.
xiaoshu
- 基于Verilog的小数分频,带testbench，可直接modelsim仿真-Verilog-based fractional divider with testbench, modelsim simulation can be directly
div_clk
- verilog实现任意时钟分频，简单明了，打开modelsim-change directroy-do sim .do 即可-Achieve any clock divider, simple, open modelsim-change directroy-do sim. Do to
fsm_seq_det
- verilog 状态机实现序列检测。简单明了，打开modelsim-change directory -do sim.do 即可-State machine sequence detection.