搜索资源列表
Experiment02
- FPGA黑金开发板实验教程，实验2的源代码。实验手册见《verilog那些事儿》-Black gold FPGA development board test tutorials, experiment 2 source code. Laboratory manual, see " verilog that thing"
Experiment03
- FPGA黑金开发板实验教程，实验3的源代码。实验手册见《verilog那些事儿》-Black gold FPGA development board test tutorials, experiment 3, the source code. Laboratory manual, see " verilog that thing"
VerilogHDL-na-xie-shier-REV1.0
- 网上声誉甚高的FPGA黑金开发板教程《verilog HDL那些事儿》。非常好的FPGA入门书籍。-Online high reputation of the FPGA development board tutorial black gold " verilog HDL that thing." FPGA very good introductory book.
VerilogDesignand-test_PdfPCode
- Verilog 设计与验证源码+PDF，经典教程，对与RTL和状态机的理解有很大帮助，适合FPGA开发工程师。-Verilog design and verification source+ PDF, classic tutorial, and state machine understanding of RTL helps a lot, suitable for the FPGA development engineers.
Verilogtutorial
- 《Verilog数字系统设计教程》，很不错的一本学习verilog的书，推荐给大家-a good book for learning verilog, recommend to you!
cpu_verilog_vhdl
- CPU核verilog、VHDL实现（两个8051带文档 ， or12000 ） 以及cpu设计教程-Personal collection of the CPU core (with two 8051 documents, or12000) plus cpu design tutorials
wangjinming-Verilog100
- 王金明：《Verilog HDL 程序设计教程》verilog 100例-Wang Jinming: "Verilog HDL programming tutorial" verilog 100 examples
Chapter-2
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-3
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-4
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-5
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
FPGA-lasted-7-days-Altera-v1.0
- verilog 语言，通向FPGA之路---七天玩转Altera 3本，高人总结，对fpga开发很有帮助！经典，教程，vhdl，笔记。-Verilog language, superior to summarize and fpga development to have the help very much! Classic, tutorials, VHDL, notes.
Verilog_classic-tutorial
- Verilog_经典教程,非常好的学习资料，对初学者很有用，值得好好看看Verilog语言编程-Verilog_ classic tutorial, very good learning materials, useful for beginners, it is worth a good look at
VerilogHDL
- 王金明：《Verilog HDL 程序设计教程》-Verilog HDL
examples
- Verilog HDL 程序设计教程；王金明-Verilog HDL programming tutorials
VerilogHDL-instructions-in-HUAWEI
- 华为内部使用的Verilog HDL培训入门教程，适用于初学者学习使用-Verilog HDL material in Huawei,suitable for Verilog Greenhands
ASICinoutport
- VERILOG设计双向端口的详细教程，里面有几个详细例子-VERILOG design a detailed tutorial of the bi-directional port, there are several detailed examples
program
- verilog 程序设计教程，方便初学者学习参考，通俗易通，方便理解-verilog programming tutorials, easy for beginners to learn the reference to popular ETS, to facilitate understanding
Verilog_HDL
- verilog HDL语言设计的教程，比较详细-verilog HDL language design tutorials, more detailed
risc_cpu-OK
- 夏宇闻 verilog数字系统设计教程源码 第二版，实现了简单的RISC CPU。印刷版有误，已改正。- A simple RISC CPU Verilog HDL source code. Work well.