搜索资源列表
div5
- 用verilog描述的任意分频器，包括奇偶分频。-Any divider verilog descr iption, including the parity divide.
fp
- 用FPGA Verilog 语言编写的一个简单的分频器，内部有详细的中文注释，希望对初学者有益。-The FPGA Verilog language written in a simple divider, there are detailed notes in Chinese, hope useful for beginners.
Verilog1
- 实现了cic分频功能，分频系数D可变2~32，代码用verilog编写，其中输入数据写入主程序中，便于后人testbench的编写-Cic divide divider coefficient D variable from 2 to 32, the code is written in verilog input data is written to the main program, to facilitate future generations testbench preparation
Clk_Divider
- System Verilog Clock Divider module done with impementation, contains the implementes modules inside too.
vclkdiv
- 在QuartusII软件中用Verilog HDL编写的关于分频器的源代码-With in QuartusII software written in Verilog HDL source code of the divider
div16d8
- 16位除以8位除法器，Verilog HDL语言-16 divided by 8 divider, Verilog HDL language
div_nonrestoring
- 用verilog 实现的除法器 ，被除数32位 除数为16位-Divider using verilog realize the dividend 32 divisor is 16
divider_VERILOG
- 采用VERILOG实现硬件除法器。提供RTL代码和仿真文件。-Achieved using VERILOG hardware divider. Provide RTL code and simulation files.
verilog_fenpin0
- 这是一个verilog分频代码，代码比较简洁.-This is a divider verilog code, the code is relatively simple.
SUANSHUJISUAN
- 通过verilog hdl实现加法器乘法器，除法器的设计-Achieved through verilog hdl adder multiplier, divider design
a
- 用verilog实现除法器，调用了ip核，不仅有源代码，还有测试程序的时序编写-verilog ise divider
zs
- 基于fpga的数字频率计，verilog编写，可修改闸门宽度0.1s/1s/10s，可测频率1hz~1mhz，包含整个工程，内部分频模块为了仿真方便改小了，后面注释为50mhz晶振下的分频值，可根据需要自行修改-Fpga-based digital frequency meter, verilog prepared to modify the gate width 0.1s/1s/10s, measurable frequency 1hz ~ 1mhz, contains the entire
fenpin
- verilog语言编写的分频程序，可以通过defpram实现任意整数任意占空比分频，有详细注释-divider verilog language program can be achieved through defpram arbitrary integer divide any duty, detailed notes
fenpin5
- 用verilog语言实现的分频器，开发环境是Quartus2 7.2版本-Divider using verilog achieve
FREQMODN
- 描述在verilog中除頻電路的verilog代碼-Described in verilog verilog code divider circuit
signed_integer_divider_latest.tar
- VERILOG IMPLEMENTATION OF SIGNED INTEGER DIVIDER
xiaoshu
- 基于Verilog的小数分频,带testbench，可直接modelsim仿真-Verilog-based fractional divider with testbench, modelsim simulation can be directly
div_clk
- verilog实现任意时钟分频，简单明了，打开modelsim-change directroy-do sim .do 即可-Achieve any clock divider, simple, open modelsim-change directroy-do sim. Do to
divider_32bitdivby16bit
- verilog代码实现的32位除以16位无符号整数除法器，在别人8位除法器的基础上改进完成，32个时钟周期完成一次运算。-verilog code for 32-bit divided by 16-bit unsigned integer divider it s based on other guy s 8 bit divider verilog code. it need 32 clock cycles to complete an operation.
gen_divd
- FPGA分频器，verilog语言版本，通过实例化参数实现任意整数倍分频-FPGA divider, verilog language version, by instantiating an arbitrary integer multiple parameters Divide