搜索资源列表
singnal
- VHDL实现通用通信信号源,包括sin,cos,方波,三角波,BPSK,GMSK,ASK,16QAM等信号的产生以及DDS,PLL的VHDL系统代码-VHDL implementation of universal communication sources, including sin, cos, square, triangle, BPSK, GMSK, ASK, 16QAM and other signal generation and DDS, PLL system, the VHDL
sram64kx8
- 基于VHDL的一种SRAM模块,简单,但是可参考性强-A VHDL-based SRAM modules, simple, but can be refered strongly
Viterbi
- 实现VHDL的维特比译码 -VHDL Viterbi decoding to achieveVHDL Viterbi decoding to achieve
wave
- 可控脉冲发生器的VHDL源代码。设计文件加载到目标器件后,按下按键开关模块的S8按键,在输出观测模块通过示波器可能观测到一个频率约为1KHZ、占空比为50 的矩形波。按下S1键或者S2键,这个矩形波的频率会发生相应的增加或者减少。按下S3键或者S4键,这个矩形波的占空比会相应的增加或减少。-Controllable pulse generator of the VHDL source code. Design documents loaded to the target device and p
LIP1601CORE_des_3des
- DES & 3DES VHDL & Verilog code
DCM
- Xilinx公司诸多型号开发版中的一个模块,能够实现1到16次倍频和分频等功能。使用时现在ISE集成开发环境下利用VHDL进行例化。本文档为个人学习总结-Xilinx, a number of models developed version of a module, be able to achieve 1-16 times multiplier and divider functions. ISE now use integrated development environment for
pci_core.tar
- vhdl 写的 PCI IP核程序,已经过测试-pci ip core
Fredevider_n
- 任意N偶数倍频率分频器VHDL语言,编译器MAX_PLUS2-Any even multiple of the frequency divider N VHDL language, compiler MAX_PLUS2
Learning-VHDL-with-example
- 学习VHDL,从入门到精通,包括学习的书籍资料和相关例程分析。-Learning VHDL, from entry to the master, including the study of books, information and case studies.
multiplexer
- 几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code
turbodecoder
- 用vhdl实现turbo码的迭代解码,转某N人的程序-Using vhdl implementation of iterative decoding turbo codes, transfer of a person' s procedures for N
FPGAuartdebug
- FPGA串口界面调试程序,用VHDL语言实现-FPGA serial debugger interface, using VHDL language implementation
iic
- 单片机和cpld通信中的用vhdl编写的cpld源程序代码-Cpld single-chip computer and communications cpld prepared using vhdl source code
PCK_CRC32_D8
- VHDL实现的8位数据,CRC32的实现代码,简单实用-VHDL achieve 8-bit data, CRC32 implementation of the code, simple and practical
24_bit_register
- 自己使用VHDL语言编写的24位寄存器.主要用于DDS中-24bit_register
DIANZIRILI
- EDA 用VHDL语言做的电子万年历,有全套的代码还有仿真-EDA using VHDL language to the electronic calendar, there is a full set of code there are simulation
CRC32_DATA16
- IEEE 802.b CRC32 VHDL
01.ISE8.2
- 这个是我用的合众达试验箱里面的资料。合众达试验箱里面集成的是xilinx的virtex4,这个是在ise环境中审计的程序,包括led,da/ad转换实验,键盘实验,以及rtc读取和lcd显示等。-vhdl programs that used by xilinx virtex4
dac0832
- 关于CPLD程序,采用VHDL语言实现DAC0832的时序控制-CPLD about procedures, the use of VHDL language implementation of the DAC0832 Timing Control
vhdl-examples
- VHDL写的100多个经典例子,适合初学者。包括分频器,简易时钟等-VHDL written more than 100 classic example, suitable for beginners. Divider, the simple clock