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Pld_lab4
- stop watch in vhdl using MAXII development board.
cnt8bc
- 8位加减带异步复位计数器，使用双向输入管脚- Design an 8-bit up and down synchronous counter in VHDL with the following features: The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered. The counter is with an asynch
sdram_vhd_134
- Xilinx Sdram控制器VHDL源代码-Sound code of Xilinx Sdram Controller based on VHDL
VHDL
- 8位相等比较器含源代码，用VHDL语言编写，具体很高的实用性，供读者参考-8, phase comparator, such as with the source code, using VHDL language, the specific relevance of a high for the reader is referred to
liftvhdl
- 四层电梯vhdl 1、 每层电梯的入口处设有上下请求开关，电梯内设有乘客到达层次的停站请求开关。 2、 设有电梯所处位置指示装置及电梯运行模式（上升或下降）指示装置。 3、 电梯每秒升降一层。 4、 电梯到达有停站请求的楼层后，经过1s电梯打开，开门只是灯亮，开门4s后，电梯门关闭（关门指示灯灭），电梯继续运行，直至执行完请求信号后停在当前楼层。 5、 能记忆电梯内外的所以请求信号，并按照电梯运行规则依次响应，每个请求信号保留至
fifo的vhdl原代码
- 本文为verilog的源代码-In this paper, the source code for Verilog
VHDL-clock
- VHDL的程序设计模块，很有用那个，密码锁。-for vhdl！！
ledwater
- 使用VHDL语言编写的跑马灯程序，利用Quartus2可以对其编译下载-The use of VHDL language Marquee procedures, the use of their compiler can download Quartus2
FIFO_Design
- 一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation
5
- 用VHDL语言实现电子钟-Using VHDL language electronic bell
ALU_ise10migration
- It s vhdl source code for 32 bit ALU.
FDWT
- it explains the ID DWT concepts. and the codes are in VHDL and MATLAB
VHDLprogram
- VHDL的程序包，包括LED控制，LCD控制、DAC0832接口电路、URAT、FSK\PSK\MASK调制、波形发生器等。适合工程参考-VHDL package, including the LED control, LCD control, DAC0832 Interface Circuit, URAT, FSK \ PSK \ MASK modulation, such as waveform generator. Reference for the project
FSK-VHDL
- FSK调制与解调VHDL程序及仿真，仿真通过-FSK modulation and demodulation process, and VHDL simulation, simulation by
lcd
- 利用FPGA驱动LCD显示中文字符的VHDL程序-Use of FPGA-driven LCD display Chinese characters of the VHDL program
CPU
- 16位简单cpu用VHDL语言实现。里面有好几个的》-16-bit cpu with a simple VHDL language. There are several of the "
digitalclockvhdl
- EAD设计VHDL语言环境数字时钟数码管显示方案，包括时间设置、调整等。-VHDL language environment EAD design digital digital clock display, including time for setup, adjustment.
freerisc8_11
- 一个基于VHDL 的简单8位CPU的IP core核心代码-VHDL based on a simple 8-bit CPU core code of the IP core
NCO_sin
- 介绍了压控震荡器(VCO)的设计，压缩包里面有VHDL语言编写的代码，在仿真器上可以实现仿真结果，非常不错 -The VHDL code of VCO