搜索资源列表
i2c_master
- Avalon I2C master. Ready to use with SOPC.
mvbc3_ise6_bak
- MVBC VHDL代码..实现多功能车辆总线的通信-MVBC VHDL code. . Multi-purpose vehicle bus communication
m15
- 扩频通信M序列,编码,通用VHDL语言-M sequence spread spectrum communication, coding, generic VHDL
LAC_adder16
- 十六位超前进位加法器,Verilog HDL-16-ahead adder, Verilog HDL
led_pwm
- 用硬件描述语言实现的灯控IP核,可实现至少256种颜色的真彩变换。-using Hardware Descr iption Language lights control IP core can achieve at least 256 colors transform the sleekly.
数字边沿鉴相器
- 数字边沿鉴相器 verilog源程序 -figures for 2500 phase-2500 verilog source digital phase detector verilog source
wtut_vhd
- 这是一份FPGA例程,敬请参考,软件环境ISE8.2-FPGA routines locations reference software environment ISE8.2
ClockOut
- 通过VERILOG编程,实现FPGA任意整数分频的源代码-through verilog programming, FPGA arbitrary integer frequency of the source code
DDS_Power
- FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波,方波,三角波,斜波,以及四种波形的任意两种的叠加,以及四种波形的叠加;通过控制频率控制字C的大小,以控制输出波形频率,实现1Hz的微调;通过地址变换实现波形相位256级可调;通过DAC0832使波形幅值256级可调;通过FPGA内部RAM实现波形存储回放;并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table thr
NumClock
- 基于Altera公司系列FPGA(Cyclone EP1C3T144C8)、Verilog HDL、MAX7219数码管显示芯片、4X4矩阵键盘、TDA2822功放芯片及扬声器等实现了《电子线路设计• 测试• 实验》课程中多功能数字钟实验所要求的所有功能和其它一些扩展功能。包括:基本功能——以数字形式显示时、分、秒的时间,小时计数器为同步24进制,可手动校时、校分;扩展功能——仿广播电台正点报时,任意时刻闹钟(选做),自动报整点时数(选做);其它扩展功能——显示年月日(能处理
lattice_sdram_source_code
- lattice sdram 控制器的源码,VHDL语言编码 包括仿真文件-lattice sdram controller source code, including VHDL simulation document coding
fcout
- 频率计源代码,性能很好,verilog写的,顶层原理图,底层语言写的,效果很好,开发环境为quartus-Cymometer source code, good performance, verilog written by the top diagram, the bottom language was written. good effect, and development environment for quartus
more111
- 本程序对输入的任意多个二进制数字进行判别(0和1的个数)-procedures for the importation of arbitrary binary figures for the number of discriminant (0 and 1 Number)
mux16_1
- 本程序实现了对输入数路的16选1功能,需要的同志可以研究研究,共同进步-the realization of the import of a number of routes 16 election a function, the comrades need to be studies, and common progress
shift111
- 本程序实现数字的前向或者后向移动功能,大家可以参考以下-the program prior to the figures, or after moving to function, we can refer to the following
cmos_FPGA
- 采用Verilog语言,实现了FPGA控制视频芯片的数据采集,并将数据按帧存储起来-Verilog language, to achieve control of the FPGA chip video data acquisition, Data will be stored up by frame
verilog_Divide
- 这是我下的一个用verilog实现的除法代码-This is the one I use to achieve the verilog code division
VGA_Controller
- 在AlTEA的DE2平台上用VerilogHDL实现的VGA控制模块-AlTEA in the DE2 platform with VerilogHDL achieve VGA Control Module
ISP1362_IF
- ALTERA上DE2平台的USB(ISP1362)模块的底层Verilog描述。-Altera DE2 platform on the USB (ISP1362) module bottom Verilo g descr iption.
ddsuart
- DDS(直接数字频率合成器)的整个工程文件,已在板子上运行通过,实现了正弦波、方波、三角波的调幅、调频,尚未实现调相,希望有志同道合者可一同完善!-DDS (direct digital frequency synthesis), the whole project documents, the board has been run through, achieved a sine, square, triangle wave amplitude, frequency, phase modula