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FPGA-digital-circuit-design
- < FPGA数字电子系统设计与开发实例导航> 一书的代码，FPGA数字电子系统设计与开发实例导航,用硬件描述语言编写的，I2C,UART,USB，VGA，CAN-BUS，网络等等的书籍配套原代码。。。。 使用方法： 1.拷贝到硬盘。 2.用ISE创建项目，分别加入各个代码文件，即可。
adder215
- 有关于加法器的vhdl编程，是用赛灵思的fpga实现的，可以在赛灵思网站上找到更具体的说明-Adder on the vhdl program is the use of the Xilinx fpga achieve. Xilinx website can be found on more specific details of their
Project1-DDS
- 直接频率和成DDS，可以在Altera的FPGA下载实现-directly into DDS frequency and can be downloaded from Altera FPGA Implementation
TC2345899
- 一个非常齐全的数字电路芯片资料库，内有将近一千个器件资料。-a very complete circuit chip digital database containing nearly 1,000 device information.
lookup_multi
- //4×4 查找表乘法器 module mult4x4(out,a,b,clk) output[7:0] out input[3:0] a,b input clk reg[7:0] out reg[1:0] firsta,firstb reg[1:0] seconda,secondb wire[3:0] outa,outb,outc,outd always @(posedge clk) begin firsta = a[3:2] se
Verilog_Development_Board_Sources
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code q
V+m511
- M序列编码-M coding sequence
dpll0227
- DPLL同步提取有一定效果-DPLL simultaneously extract a certain effect 11111111111111111111111
3fast_des
- 一个快速实现3des的算法，分别用vhcl和Veriloge语言进行编写，很实用-a rapidly 3des algorithm respectively vhcl Veriloge language and prepared very practical
81i_radix2_xfft1024_v3_2
- xilinx FFT using ip core project navigator-xilinx ip using FFT core project navigator
sdram_verilog
- 这是使用VERILOG语言，基于MICRON公司的SDRAM开发的SDRAM接口逻辑-verilog This is the use of language, MICRON-based company's development of the SDRAM SDRAM interface logic
traffic2
- 用verilog编的小程序,希望对需要的人有所帮助-verilog series with a small procedure, and I hope to the people in need some help
verilogled
- cpld-epm7128stc100-10驱动四位LED结果显示1234-cpld - epm7128stc100-10 drive four LED 1234 results
cpldPWM
- verilog HDL 编写的PWM，是初学CPLD者入门Z资源，epm7128stc100-10-verilog HDL prepared by the PWM, is a novice CPLD Getting Started Z resources, epm7128stc100-10
key1
- Altera CPLD矩阵键盘一个很不错的Altera芯片程序-Altera CPLD matrix keyboard is a good Altera chip process
seg71
- 这是一个很不错的CPLD数码管测试程序,从这个程序个大家得很多启发-This is a very good CPLD digital control testing procedures from the process - we have a lot of inspiration
traffic
- ＣＰＬ串口程序经过调试希望大家喜欢，很好呀大家慢慢来下载吧-CPL after serial debugging procedures hope you like, ah well we slowly download it
nios_uart
- 基于Nios II的串口通信，在quartus的开发环境中进行的实验-based Nios II Serial Communication in quartus development environment for the conduct of the experiment
SVGA_quartus
- 在开发板上实现svga条形信号发生器的源代码，是在quartus II 6.0的开发环境中运行的-achieved in the development of board svga strip signal generator source code, in quartus II 6.0 development environment running on
dds_ise7.1_su
- 用Verilog语言实现信号发生器，包括AM，FM,PM，ASK,PSK,FSK调制。-using Verilog language signal generator, including AM, FM, PM, ASK, PSK, FSK modulation.