搜索资源列表
manydecoders_V
- 各种解码译码电路模型的VerilogHDL描述-various decoder decoding circuit model of Verilog HDL descr iption
Verilogexamples
- Verilog变成100例，里面包含了Verilog编程中常见的一些例子，对于新手还是很有帮助的。-Verilog into 100 cases, they include a Verilog Programming common examples is very helpful for the novice.
8LEDverilog
- //led.v /*------------------------------------- LED显示模块：led(CLK,AF,ADDR,DATA) 功能： 显示 注意事项： 8位LED 参数： CLK:扫妙时钟输入，推荐1kHz AF:数码管输出，a～h ADDR:数码管选择位数出，0~2 DATA:显示数据输入0~9999 9999 编写人： 黄道斌 编写日期： 2006/07/13 ----------------
sram
- sram 读写小程序，用verilog编写的，请各位高手指教-SRAM read and write small programs using Verilog prepared, please enlighten you master
DE2_i2sound
- DE2_i2sound.rar，大家快来下啊，做好了的IP核-DE2_i2sound.rar, everyone is breaking under ah, do a good job of the IP Core
DE2_Top
- DE2_Top.rar，做好了的IP核，大家开来下啊！-DE2_Top.rar, do a good job of the IP core, open to everyone under ah!
color_proc333
- 基于fpga的MJPEG编码,用硬件描述语言vlogic写的-they simply based on the JPEG coding, using hardware descr iption language to write the vlogic
countqi
- 计数器 同步异步预置数清零 verilog hdl 编写-Asynchrony preset counter reset the Verilog HDL few prepared
xapp290
- 从Xilinx网站上下的，学习FPGA部分动态重配置很好的例子。-from across the Xilinx website, learning some FPGA dynamic reconfigurable good example.
verilog100
- 有很多例子及测试代码，对初学者很有帮助，很容易上手-a lot of examples and test code, useful for beginners, it is easy to get started
RS_decoder
- rs编码vvhdl 希望能通过 我不晓得具体对大家有用否 希望懂rs编码的多多交流 -rs coding vvhdl I do not want to be able to know the specific useful whether you want to understand a lot of coding rs exchange
eathnet
- 百兆以太网mac和mii的vhdl源程，作IPcore的时候非常有用-Fast Ethernet MII and the VHDL source way for IPcore very useful when
I2CSlave
- Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave
lru_new
- 采用LRU替换算法。这种算法选择最久没有被访问的块作为被替换的块。 为了实现LRU算法，要在块表中为每一块设置一个计数器（cnt0，cnt1，cnt2，cnt3，）。计数器的长度为2位。-using LRU replacement algorithm. This algorithm to choose the most long visit is not being replaced as a block by block. To achieve LRU algorithm, in bloc
m16550a_verilog_rtl
- mentor UART IP verilog源码 以通过验证.-mentor UART IP verilog source to the test.
FSM_Westor
- 状态机得用法，可以帮助新手了解状态机得用法以及掌握用途-state machine in use, and can help newcomers understand the state machine in use, and control purposes
lcd12
- 基于ＡＬＴＥＲＡ公司的ＤＥ２的ＬＣＤ显示程序，一起学习．非常好的资料，也非常难得．是我参加培训时所得-the DE2 LCD display program, learning together. Very good information, and they are extremely rare. I receive training
usb1.1phy
- USB 1.1 PHY的代码，verilog语言 USB 1.1 PHY的代码，verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language
randn
- 随机序列发生器,是一个m序列,生成函数都写在里面,位宽为4,可以改变!-random sequence generator, m is a sequence, generating function will be included in the inside, for four bit-can be changed!
permute
- 交织器的一部分,可以生成交织索引函数,如果加上一个随即序列发生器就可以组成一个交织器 了!-interleaver part of the index can be generated intertwined function, If coupled with a sequence generator immediately on the formation of a interleaver!