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multipliers
- 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
shift_registers
- 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
sum_of_products
- 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
20064316212158
- 要如何区别呢？执行公用程式‘file’（例如，file /bin/bash）就对了。就ELF的程式而言，萤幕上显示出来的讯息会含有ELF的字眼；如果说是a.out的，讯息内会箝有 Linux/i386的字样。 -to how to distinguish? Implementation utility 'file' (for example, the file / bin / bash) on the right. On the ELF programs, the screen
vhdl-com
- 一些vhdl的常用程序，包括键盘扫描-instantiate some common procedures, including scanning keyboard, etc
verilog_UART
- UART verilog hdl 实现-UART Verilog HDL achieve
UART_BooQuai
- FPGA上实现UART串口原程序，在ISE6编写的-FPGA serial UART to achieve the original procedure, the preparation of the ISE6
collectionOfImageAndinterpolation
- 该系统是一个实现图像数据采集以及对图像数据的插值处理，供其它系统进一步处理或显示的系统。具有一定的通用性，适合大多数CMOS图像传感器接入。1准确、适时的数据采集，尽量减少延迟 2采集模块具备一定的数据缓冲功能 3快速有效的数据插值 4使用较少的逻辑器件和存储器 5代码的可读性要强 -The system is a realization of image data acquisition and the image data interpolation, other system for
FIR_1
- FIR滤波器的verilog实现，实现6级流水线的程序设计。-FIR filter Verilog, has implemented six lines of program design.
xapp195
- signed_mult乘法器通常用于DSP设计。但由于赛灵思的FPGA架构中包含有-signed_mult multiplier is used DSP design. But Xilinx FPGA architecture contains
sdramcore
- sdram控制的内核，高手编的，已经调试过了，没有错误-SDRAM control of the kernel, the top series, has been tuned, no errors
sram_verilog
- 告诉图形采集 verilog代码 很简单的 第一次发-tell graphics Acquisition Verilog code is very simple first grant
veriloghdl135
- vhdl的学习资料，教程，一起进步，共勉-VHDL learning materials, curricula, progress together, share!
color_space_converter
- verlog 编程 色彩空间转换 有测试文档-verlog programming color space conversion is testing documents
ad_DCT
- verilog 编程 有测试文档 基于查表结构实现 离散余弦变换dct 来源：opencores -Verilog Programming is based on the test documents Lookup structure for a discrete cosine transform Extra Source : opencores
entropy_coding
- 用verilog 描述的嫡编码(entropy coding) 应用于图像压缩编码 有测试文档 -using Verilog His descr iption of coding (entropy coding) for image compression test files are encoded
run_length_coding
- 用verilog 编写 应用于图像压缩编码中 使用行程长度编码(run lengthencoding,RLE)对交流系数(Aa)进行编码。-using Verilog prepared for image compression coding using length encoding (run leng thencoding, RLE) on the exchange coefficient (Aa) coding.
verilog_jpeg
- 用verilog 描写 应用于数字图像压缩系统--jpeg 有测试文档-using Verilog descr iption applied to digital image compression system -- a test jpeg files
PCIarbitration
- 这是PCI 仲裁机制的VHDL源码，它实现了PCI仲裁机制。-PCI arbitration mechanism VHDL source code, it achieved a PCI arbitration mechanism.
desimplementation
- 一个关于DES算法的verilog语言实现,包括了各个实现模块以及测试模块-a DES algorithm on the Verilog language, including the realization of the various modules and test modules