搜索资源列表
Verilog_add4
- add4 verilog code -add4 Verilog code
dct_mac
- dct verilog code for image -Extra Verilog code for image
trafficontrol
- 使用verilog编写的交通灯控制程序，各方向通行时间可调，绿灯5s闪烁，在maxplus下调试通过，附仿真波形，在EP系列实验板上测试成功-use Verilog prepared by the traffic lights control procedures, the passage of time adjustable direction, green 5s flickered in maxplus under debugging, simulation waveforms with t
i2c8
- I2c 总线测试程序,经过多次验证的.包括读写模式(第一次上传)-I2c bus testing procedures after several tested. Including reading and writing mode (the first uploading)
YCbCr_to_rgb
- 颜色空间转换代码,ycbcr对rgb的转换verilog代码.YCBCR的格式是ITU601格式.-color space conversion code, RS right rgb conversion Verilog code. YCBCR format is ITU601 format.
frame_decode_and_encode
- 一个用Verilog编写的编帧、解帧及码速匹配的程序，相当经典-Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!
WM8731
- 高品质音频编解码器WM8731的Verilog使用程序。-high-quality audio codec WM8731 Verilog procedures.
verilog_vga
- 用verilog HDL 语言写的在显示器上显示图案的源程序-with Verilog HDL language written on display in the pattern of the source
verilog_lcd
- 用Verilog HDL 语言写的在LCD液晶上显示文字的源程序-with Verilog HDL write on the LCD display text of the source
Altera_uart_VHDL
- FPGA/CPLD应用,uart通讯VHDL原码.-FPGA / CPLD applications, UART communications VHDL source.
Altera_uart_Verilog
- FPGA/CPLD应用,uart的Verilog HDL原码-FPGA / CPLD applications, UART Verilog HDL source
wavefetch
- ModelSim的波形比较的功能可以将当前仿真与一个参考数据（WLF文件）进行比较，比较的结果可以在波形窗口或者列表窗口中查看，也可以将比较的结果生成一个文本文件-ModelSim waveform can be compared to the current functional simulation with a reference (WLF paper ), the results can be compared in the waveform window or window List
CORDIC01
- CORDIC算法的硬件实现 用的verilog语言-CORDIC algorithm Hardware Implementation of the Verilog language
Cpu_model
- Verilog HDL编写的CPU模型，很经典，比较通用-Verilog HDL prepared by the CPU model, classic, more generic
bfm
- Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
clock2001
- 时钟模块之一：二进制转BCD码verilog源代码FPGA advantage编程环境-clock module : BCD switch binary source code Verilog FPGA advantage programming environment
crcDecode
- 比较完善的CRC编码VerilogHDL描述-more perfect descr iption of CRC coding VerilogHDL
PAOBIAO_V
- 带音乐功能的跑表VerilogHDL描述-music with the stopwatch Verilog HDL descr iption
MutiPipeACC
- 多通道的ACC设计VeerilogHDL描述-multi-channel design VeerilogHDL ACC Descr iption
gatediscrip
- 各种门电路模型的VerilogHDL描述-various gates model of Verilog HDL descr iption