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HALF-ADDER-VHDL
- 用硬件描述语言编写的8位全加器代码，很实用通过对代码的编译和波形检测显示出此设计也是完全符合要求的，并且和设计的电路图一样，也达到相同的效果。-Using hardware descr iption language preparation 8 bits QuanJia implement code, is very practical through the code compiler and waveform test shows the design is fully meet the r
Full_adder
- VHDL新手入门：全加器的实现及仿真，输入量为两个不同频时钟-VHDL Getting Started: full adder implementation and simulation, input clock frequency for the two different
A-QuanJia-device-design
- 一位全加器设计，，二进制设计，，同步二进制计数-A QuanJia device design
adder4_head
- 4位二进制并行加法器。现在普遍使用的并行加法器是超前进位加法器，在几个全加器的基础上增加了一个超前进位形成逻辑，以减少由于逐步进位信号的传递所造成的时延。-Four binary parallel adder. Now commonly used parallel adder is advanced in several adder, carries on the basis of QuanJia device adds an advanced form logic, to reduce car
mux16
- 在乘法器电路中，乘数中的每一位都要和被乘数的每一位相与，并产生其相应的乘积位。这些局部乘积要馈入到全加器的阵列中（合适的时候也可以用半加器），同时加法器向左移位并表示出乘法结果。-On time-multiplier circuit, in each of the multiplier to each BeiChengShu paleotopography, and produce its corresponding product bits. These local product will
adder
- 加法器是产生数的和的装置。加数和被加数为输入，和数与进位为输出的装置为半加器。若加数、被加数与低位的进位数为输入，而和数与进位为输出则为全加器。-The number of adder is produced and device. Addend and BeiJiaShu as input, and the device for output with binary for half a gal device. If BeiJiaShu and low addends, into digits
jiafaqi
- 加法器是产生数的和的装置。加数和被加数为输入，和数与进位为输出的装置为半加器。若加数、被加数与低位的进位数为输入，而和数与进位为输出则为全加器。-Adder is generated and the number of devices. Addend and the summand input, and digital and carry the output device is a half adder. If the addend, the progress of summand bits
TEST
- I2C总线的实现，一个基于计数器的加法器。其中使用三个寄存器来实现计数器的功能，再由两个半半加器实现全加器额功能。-realize the inter-integrated circuit bus
f_add
- EDA实验中的全加器的VHDL语言的实现，包含半加器、全加器、JK触发器、D触发器以及50m分频的源程序-EDA test full adder in VHDL language implementation, including the half adder, full adder, JK flip-flop, D flip-flop and the frequency of the source 50m
adder_32bit
- 以ISE为平台，用Verilog编写的32位全加器模块，只需在Top模块中调用即可-The ISE as a platform, written with Verilog 32-bit full adder module, simply call the module to Top
chengxu
- EDA实验程序实现8位全加器，999计数器数码管显示以及频率计数器显示的源程序。。。以经过测试。-EDA experimental procedures to achieve 8-bit full adder, counter 999 and frequency counter digital display shows the source. . . To be tested.
full_add
- 全加器，基于原理图设计的全加器。经过时序仿真验证-Full adder, based on the schematic design of the full adder. After timing simulation
Sainty2
- 里边有一个半加器。、一个全加器、一个触发器和一个无符号4乘4的乘法器程序，可以完成4位无符号数相乘-Inside there is a half adder. , A full adder, a flip-flop, and an unsigned 4 by 4 multiplier process can be completed by multiplying the number of 4-bit unsigned
h_adder
- 一个二位全加器的VHDL实现程序，能够完美在Quartus上运行-a h_adder write in VHDL，can work well on Quartus
sy1
- 里面附有两个VHDL实验，分别是一位全加器和计数译码显示模块-Experiments with two VHDL which, respectively, a full adder and the counter display module decoding
quartus
- 通过使用4位全加器和4位比较器以及相关组合逻辑的使用并结合BCD码加法规则构成4位BCD码加法器。-Through the use of four full adder and 4-bit comparator and associated logic of the use and combination with BCD adder rules constitute four BCD adder.
ep2c35_3.8_full_add
- 这个程序用verilog硬件语言编写。用来在FPGA内实现全加器。并且可以将输出显示在外部LED灯上等。-this program is writen by verilog HDL.it is the full adder for FPGA.users can read the result from the LEDs.
quanjiaqiheDchufaqi
- 设计一个全加器元件，再用该元件连成4位二进制加法器 设计一个D触发器元件，再用该元件连成4位寄存器 -Design a full adder component, then the component with a 4-bit binary adder design a D flip-flop element, then the components together into four registers
four
- 大学VHDL实验科目报告四位全加器设计报告-University of VHDL test subjects reported four full adder design report
full_adder-and-half_adder
- 在Quartus II中用VHDL语言编写的全加器与半加器程序，全加器是调用半加器来实现的。-In the Quartus II VHDL language using the full adder and half adder program, full-adder is called a half adder to achieve.