搜索资源列表
c51
- 51单片机，USB，触摸，TFT,的等综合应用，高级别。（usb+flash+touch+tft+ram综合测试）-51 single-chip, USB, Touch, TFT, integrated applications (usb+ flash+ touch+ tft+ ram General Test)
Verilog_NBA
- Verilog非阻塞赋值的仿真/综合问题-Non-blocking assignment Verilog simulation/synthesis
20081129464173846
- 介绍Verilog HDL, 内容包括： – Verilog应用 – Verilog语言的构成元素 – 结构级描述及仿真 – 行为级描述及仿真 – 延时的特点及说明 – 介绍Verilog testbench • 激励和控制和描述 • 结果的产生及验证 – 任务task及函数function – 用户定义的基本单元(primitive) – 可综合的Verilog描述风格-Introduced the Verilog HDL, in
verilog
- 可综合的Verilog语法（剑桥大学，影印）-Can be integrated Verilog syntax (Cambridge, photocopying)
miller
- 用ISE编写的VERILOG语言的米勒解码器的检测部分，检测四种解码信号。程序通过综合，但是仿真结果有点偏差，欢迎高手指点。-ISE prepared with VERILOG language detection decoder Miller of the four decoder signal detection. Procedures through an integrated, but the simulation results is biased and expert advice
8fifo
- 可综合的 8x8 fifo VHDL 源代码-Can be integrated 8x8 fifo VHDL source code
CPU_verilog
- 一个4级流水线CPU的verilog代码，供参考学习使用，有些语句不能综合，可以通过它学习CPU的工作原理。-A 4-stage pipeline CPU' s verilog code, learning to use for reference, some statements can not be integrated, you can learn from CPU through its works.
FIFO_Buffer
- Verilog的FIFO源代码，可综合，并以运用到具体工程中-Verilog source code of the FIFO can be integrated and applied to specific projects
async_transmitter
- RS232串口发送模块，verilog编写，可综合-async_transmitter verilog module
verilog_hdl_synthesis_primer
- verilog 综合方面的教程，J。bhasker编写。-integrated in verilog tutorials, J. bhasker prepared.
simple_pic
- 一个通用中断系统的Verilog HDL描述，对想了解知道是怎么实现的读者，可以查看综合出来的电路，会有很大帮助！-A common interrupt system of the Verilog HDL descr iption of the would like to know how to achieve the readers know, there will be of great help!
VerilogSynthesis
- 有关Verilog综合方面的教程，挺有用的-(Prentice) Verilog HDL--Guide to Digital Design & Synthesis (2nd.Ed.)
crc32_4
- 实现了crc功能的verilog源程序。可以综合。-verilog code for crc
crc8
- 8位crc的verilog设计 通过仿真综合验证并已应用在工程里面 -verilog of 8bit error checkout
Verilog_HDL_Synthesis_A_Practical_Primer
- verilog综合经典教程，verilog标准制定人写的书，推荐-verilog synthesis classic tutorials, verilog standard-setting people write books, recommended
pic
- 上传的是一个PIC代码，其包含PIC完整子模块，可以进行综合，对学习PIC很有帮助-Upload a PIC code, which contains a complete sub-PIC module can be integrated, very helpful for learning PIC
keyscan_test
- 针对机械式按键存在的抖动问题，用verilog HDL编写了一个采用防抖方案并对按键次数计数的模块，已经在ISE综合通过！-Keys exist for mechanical jitter, with verilog HDL prepared a program with anti-shake button and count the number of modules have been integrated by ISE!
VerilogHDL
- Verilog HDL设计要点在前面学习的基上， 通过本章十个阶段的练习，能逐步掌握Verilog HDL 设计的要点。可以先理解样板模块中每一条语句的作用，然后对样板模块进行综合前和综合后仿真，再独立完成每一阶段规定的练习。-Verilog HDL design points in the previous study based on ten stages of practice by this chapter, can gradually grasp the main points of
top1
- verilog可综合的图像旋转模块和testbench-verilog synthesizable testbench modules and image rotation
mips
- MIPs CPU，VERILOG代码，经过QUARTUS综合，时序分析，验证无误。-MIPS CPU