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Delphi_MDI_child_inside_a_Package
- A Delphi Package is a special type of DLL, designed only to be used by Delphi applications. If your modules are developed as packages and not as DLLs, all modules will share the same memory manager, the VCL globals like Application and Screen, the sa
divide_7
- 七分频 quartus实现 有RTL图-RTL implementations seven frequency quartus map
divide_10
- 十分频 quartus实现 有RTL图-RTL is a graph realization of the frequency quartus
DFFquartus
- D触发器 quartus实现 有RTL图-D flip-flop to achieve a RTL Figure quartus
IFFT_RTL_code
- IFFT的RTL级编程，包括逆FFT转化及信息的处理。应该说比较全面，且经过验证-IFFT of the RTL-level programming, including the inverse FFT transformation and information processing. Should be said that a more comprehensive, and proven
ASIC_VHDL_FPGA_design_lectureNotes
- 这是美国普渡大学（Purdue University West Lafayette)ASIC design 的课件完整版！带事例和讲解的非常好的VHDL学习材料！含有vhdl 基础知识，设计步骤，UART, RTL,Test Bench 以及测试和调试，DEBUG等各种VHDL设计者必学知识！-This is Purdue University (USA) ECE 337 ASIC design class lecture notes! very classic! The content inc
or1200_uart
- OR1200最小系统，包括软核处理器OR1200，内存，总线，GPIO及UART的RTL实现。在SOPC2000硬件平台上实现。软件开发环境为Ubuntu，能实现SOPC2000和PC机的简单串口通信。-OR1200 minimum system, including soft-core processor OR1200, memory, bus, GPIO and UART of the RTL implementation. In SOPC2000 hardware platform. So
cppdrv2.7z
- CPP RTL For Windows Driver.
RTL
- verilog的学习很重要的教程，有很大的好处。-verilog tutorial learning is important, a great advantage.
i2c
- I2C verilog代码，支持master和slave方式，内置CPU接口-I2C verilog RTL code， support master and slave mode
KeiluV3RvRTL
- keil编译软件中关于RV和RTL的应用说明-keil compiler software applications on the RV and the RTL descr iption
RTLtoverilogcode
- 从RTL到门级电路的等价性验证设计方法的硕士论文-From RTL to gate-level equivalence checking circuit design master' s thesis
src
- FIR滤波器的设计，完整包括RTL代码、testbench等，清晰易懂。-FIR filter design, complete coverage of RTL code, testbench, etc., clear and understandable.
fir_compiler
- FIR编译器。自动生成具有用户自定参数的FIR滤波器。 在 matlab里面设计滤波器，matlab里面设计输入字长。生成的rtl代码是该文件的头部有位宽宏定义，可以自行查阅。 -FIR Compiler. Automatically generate a user-defined parameters of FIR filters. Design a filter inside the matlab, matlab which design input word length. Rtl
reset
- 这是个关于同步复位和异步复位问题的探讨，最后得出同步释放，异步复位的效果最好 文件中有编好的verilog文件工程，以及仿真结果和RTL分析图，分析的很详细-This is a synchronous reset and asynchronous reset on the issue of the conclusion that synchronous release, asynchronous reset of the best documents are programmed veril
8088verilog
- intel8088的verilog core ，完整的RTL-intel 8088 verilog core， all RTL
i2c
- I2C的RTL源码，verilog，验证过的-I2C verilog RTL
Full.adder
- Verilog的RTL级别全加器和测试平台，测试通过-Verilog RTL level full adder and test benck
GCD
- Verilog 最大公约数设计RTL级代码和芯片设计图-Verilog GCD Design and synthesis layout
Fpga_And_Cpld
- Fpga_And_Cpld设计经验总结，在数字电路的设计中，时序设计是一个系统性能的主要标志，在高层次设计方法中，对时序控制的抽象度也相应提高，因此在设计中较难把握，但在理解RTL电路时序模型的基础上，采用合理的设计方法在设计复杂数字系统是行之有效的，通过许多设计实例证明采用这种方式可以使电路的后仿真通过率大大提高，并且系统的工作频率可以达到一个较高水平。-In digital circuit design, timing design is a main indicator of system