搜索资源列表
Kbtestbench
- VHDL编写的Keyboard control使用ps2 keboard来使fgpa的led上显示键盘的二进制代码，用4个7seg来显示0-9的数字，该程序包含testbench.-ps2 keyboard controller which could enable led on fgpa to show the binary code of each key on ps2 keyboard and another four 7segment will display the number fr
Project_WorkSpace
- The code i have written is for the patent designed by Jay Hartvigsen, Tony Cheng, Eric Hoang and Buddy Broeker "JTAG/DEBUG INTERFACE". This is meant for the purpose of interfacing the controller to debug its core,this code is working fine n very so
VR
- 用于进行变量降维的matlab程序，大家可以试一试，很有效哟-Variable Reduction Testbench MATLAB modules，it is very effective， we can try, very effective ..............
rs232
- 异步串行传输的verilog hdl 功能文件以及测试文件-The verilog hdl source and the testbench of asynchronous serial transmission
I2Cdesign
- Verilog数字系统设计教程【夏宇闻】原书第十章：IIC总线接口模块设计代码包-verilog program for iic bus design. the pakege includes iic protocl master program and behavel slavle program, even includes testbench and data bat files.
C8051_mega_core.tar
- 8051单片机软核，测试代码和仿真环境，可直接上fpga使用，是一个成熟的ip核。经本人仿真以及在fpga上测试，完全正常。-8051 soft ip core, testbench, simulation environment
DSP_FIR_Lab
- DSP的FIR实验，包含三种FIR实现形式，直接型，转置型，累加型，并且附带testbench,经过modesim测试没问题。-This is DSP FIR lab, it includes there forms to implement FIR, direct form, transposed form and time mulitple form, all code has been tested on Modesim.
SystemVerilogEventRegionsRaceAvoidanceGuidelines.r
- The IEEE1800 SystemVerilog Standard includes new event regions primarily added to reduce race conditions between verification code and SystemVerilog designs. The new regions also facilitate race-free Assertion Based Verification (ABV). This pap
dual_RAM
- vhdl语言编写的双口ram及testbench,模块可以在modelsim里进行时序和功能仿真。-vhdl language of the dual-port ram, and testbench, modules, conducted in the modelsim timing and functional simulation.
VHDL_huffman_decoder
- This is a Huffman decoder with dynamic Huffcode tables. A Testbench for a jpg file is include.
fulladdertmr
- full adder tmr with testbench
four_bit_full_adder_with_time_analysis
- four bit adder with time analysis and testbench
statemechine
- We are using parameters is the test bench and passing them to the state machine using parameter passing We are using tasks to control the flow of the testbench We are using hierarchical naming to access the state variable in the state machine f
mem-ctrl-rtl
- 实现对ddr的控制，可以在fpga的仿真环境下跑程序，并有testbench可以参考-implement ddr control
ASK0908272
- 自己写的二进制频移监控程序，包含testbench,供大家参考-this is the AsK programme,including testbench
E1Tsi_TB
- TSI testbench for E1
wave
- TESTBENCH OF CARDIO SYS-TESTBENCH
rs232
- RS232的串口控制器，本程序中的每个小模块都有与之对应的testbench，模块清晰，实现结构简单。很适合Verilog编程初学者来练习！-RS232 serial port controller, the program has a small module for each corresponding testbench, module definition, to achieve simple structure. Verilog programming is suitable for
venomgen
- venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench
cordic
- altera cordic ip core, 包含文档，完整设计，以及测试向量-altera coedic ip core, including the document, whole design, and the testbench.