搜索资源列表
code_test
- uvm testbench 例子，可以在questa软件里运行，运用shell脚本，在cygwin环境中执行，非常方便-Uvm testbench example, you can run in questa software, the use of shell scr ipt, in cygwin environment, very convenient
tunjiu
- IDW inverse distance weighting method, The signal spectral analysis and filtering, This program has exceeded the performance of other algorithms.
I2C_slaver_verison3.0
- I2C从机模块，包含testbench，平台是vivado,仿真测试通过。(I2C slave module, including testbench, the platform is vivado, simulation test passed.)
sdram
- sdram的控制程序，以及相关的testbench(sdram control module)
seq
- 实现序列检测功能，新手编程，已经在modelsim里检验过了功能完整，内附模块化testbench(Sequence detection function, novice programming)
eetop.cn_UVM
- UVM 的 入门实例，一个完整的能够跑通的实例。其中包括DUT代码，Testbench代码，(UVM entry example, a complete example of running through. These include the DUT code, the Testbench code,)
New folder
- clock div testbench design and frquency division
SEQ_DETECTOR
- 这是一个四位串行数据检测器，一共有三种模式可以选择：递增（检测连续四位递增序列），递减（检测连续四位递减序列）和不变（检测连续四位不变序列）。整个设计采用同步时钟，异步复位，用米利状态机，并配置好了仿真环境和仿真文件。(This is a four bit sequence detector, including three modes that can be selected: increment mode (detecting four consistency increment data)
apb_uart
- 带apb接口的uart,带testbench，测试过，可以使用(The uart module with apb interface)
multiplier_TB
- multiplier testbench
adder_sub_TB
- adder/subtractor testbench
simulation
- 7segment testbench and velilog
simulation2
- 7segment ctrl testbench and velilog
anc dec
- encoder,decoder,testbench and run files
test
- 滤波，实现图像的滤波功能的testbench文件，可以适当参考(Filter filtering, testbench file to achieve image filtering function, you can properly refer to)
uygulama1
- verilog hdl, haladder testbench
pwm with tb final
- pwm with testbench in verilog ,synthesizable
mycode
- 这是open silicon interlaken user interface的一个driver,采用的是uvm的架构，能够实现single/dual/quad segment的配置(This is a open silicon Interlaken user interface driver, using the UVM architecture, to achieve the configuration of single/dual/quad segment)
uart
- 用Verilog实现FPGA的uart的串行通信功能，并附有testbench(The serial communication function of FPGA of UART is realized with Verilog, and Testbench is attached)
ADC_Data_Recv_Module
- 接收机测试输入信号， 生成正余弦波，采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated da