搜索资源列表
Clock_Synchronization_Module
- 数字接收机中频部分数字时钟的设计 包括matlab仿真 verilog代码、 testbench代码 以及word设计文档(Design of medium frequency digital clock in digital receiver Including Matlab simulation Verilog, testbench code, and design documents)
FFT_Module
- 接收机数字部分FFT模块的代码 包括verilog代码、 matlab仿真、 word文档 testbench 实现FFT(The code of the digital part FFT module of the receiver Including Verilog, matlab simulation, testbench Implementation of FFT)
Orthogonization_Module
- 接收机数字部分正交混频模块‘ 包括verilog代码 matlab仿真 word文档 testbench代码(Receiver digital part orthogonal frequency mixing module ' Including Verilog code Matlab simulation Testbench code)
CIC_Filter_Module
- 数字接收机cic抽取模块 抽取倍数可以选择 包括verilog代码 word文档 matlab仿真 testbench代码(CIC decimation module of digital receiver Extraction multiple can be selected Including Verilog code Word document Matlab simulation Testbench code)
ezidebug-code
- Ezidebug 支持Xilinx，chipscope 寄存器链插入、数据采集和导出、重建testbench和软件仿真验证(Ezidebug supports Xilinx, chipscope register chain insertion, data acquisition and export, reconstruction of testbench and software simulation verification)
verilog
- 8位计数器，可以实现计数器的相关功能，内涵verilog文件和testbench文件(8 bits counter,include v and testbech files ,has the ability of 8 bits counter)
float_adder
- 实现可调维度的浮点数加法运算，内涵各个子模块和testbench(Able to achieve the float numbers adding operation.)
1
- Hi This is an example of file ZIP Best regards
cy7c443
- 存储器仿真模型，建立testBench，可对cyc443存储器进行功能仿真。(TestBench memory, can establish simulation model, function simulation of cyc443 memory.)
verilog add4
- 分两部分，基于verilog的四位和八位加法器设计，用synopsys的VCS仿真工具进行功能仿真，掌握基本的makefile编写以及linux操作。(Divided into two parts, four and eight adder based on verilog design, function simulation with synopsys VCS simulation tools, master the basic makefile writing and Linux.)
fifo_test
- fifo IP测试工程，有完整的testbench 直接编译仿真即可(FIFO IP test project, completed testbench .direct compilation and simulation)
frequency divider and testbench
- a frequency divider and test bench with simulation results
sel
- fpga i/o 速率测试代码，含有testbench(FPGA i/o rate test code, containing testbench)
aes-master
- Verilog写的AES加密解密代码，带testbench。(AES encryption code written by Verilog with testbench.)
AHB RAM
- Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
apb_uart_sv-pulpinov1
- SystemVerilog 写的APB总线接口的uart 代码，带testbench.(Uart code of APB bus interface written by SystemVerilog, with testbench.)
electrical lock
- 一个用Verilog写的电子锁工程，带testbench。(An electronic lock project written in Verilog with testbench.)
ModelSim电子系统分析及仿真
- 此文档详细说明了如何利用Modelsim软件对FPGA逻辑代码进行功能仿真和时序仿真的方法，并通过相关例子进行讲解说明(This document explains in detail how to use Modelsim software to perform functional simulation and time series simulation of FPGA logic code, and explain how to use some examples.)
FP_adder
- 32 bit floating point adder with testbench
HDL_equation
- Verilog Program to implement the function f=x+yz and Testbench for all the possible inputs using For Loop