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clock
- 原创：基于VHDL语言编写的电子钟。采用模块化编写，可以调整时间，采用动态扫描显示时分秒-Original: Based on the VHDL language electronic bell. Modular prepared, you can adjust the time, dynamic scanning is displayed every minute
cvery.comdel7535899835
- 学生成绩管理 实现成绩的查询 录入多个公司的JAVA面试试题，供 ·模式识别matlab工具箱,包括SV ·文件类型：Visual FoxPro 人 ·struts2.0得例子,主要是实现s ·一个C#多线程的例子。 ·卡尔曼滤波器matlab源代码。 ·很不错的vhdl学习实例 几十 ·原版的FAT32手册,E文差的同志 ·常见的JAva面试试题，平时可 ·一个小型C语言编译器 -Student performance managem
Lift
- VHDL编写的6层电梯控制器，可在Altera的CPLD系统运行实验，内附实验报告-VHDL prepared 6-storey elevator controller in Altera s CPLD system experiment, experimental report containing
61EDA_D1051
- 用VHDL编写的计算器：能实现简单的加减乘除四则运算-Prepared using VHDL calculator: to achieve simple addition and subtraction, multiplication and division four computing
erwertwerwe
- 用VHDL编写的计算器：能实现简单的加减乘除四则运算-Prepared using VHDL calculator: to achieve simple addition and subtraction, multiplication and division four computing
SDRAM_simulation_model
- sdram的测试程序 和读写程序 vhdl语言编写的-SDRAM testing procedures and to read and write procedures VHDL language
ECCgenAndLoc
- 基于xilinx ISE环境开发的VHDL的NAND flash ECC 实现,eccGen256Byte 文件夹为ECC 产生程序，EccErrLoc文件夹为ECC错误定位程序。-Xilinx ISE environment based on the development of VHDL the NAND flash ECC to achieve, eccGen256Byte folder produced for the ECC procedures, EccErrLoc folder l
clk
- 现代电子系统课程设计 基于DDS技术利用VHDL设计并制作一个数字式移相信号发生器。 （1）基本要求： a．频率范围：1Hz～4kHz，频率步进为1Hz，输出频率可预置。 b．A、B两路正弦信号输出，10位输出数据宽度 c．相位差范围为0～359°，步进为1.4°，相位差值可预置。 d．数字显示预置的频率（10进制）、相位差值。 （2）发挥部分 a．修改设计，增加幅度控制电路（如可以用一乘法器控制输出幅度）。 b．输出幅度峰峰值0.1～3.0V，步距0
VHDL
- 状态机及其VHDL设计,详细介绍了状态机的基本结构、功能和分类，以及有限状态机的一般设计思路与方法、状态机编码方案的恰当选取、Moore和Mealy状态机的本质区别及设计实现-State machine and the VHDL design, described in detail the basic structure of state machines, function and classification, as well as finite state machine of the
serial
- 基于VHDL的串口通信 基于VHDL的串口通信-VHDL-based serial communication based on VHDL Serial Communication
vhdl
- 着个是一个8051的完整源代码，用VHDL书写。需要的可以看看，很有好处-8051 a month is a complete source code, written using VHDL. Needs can see, it is beneficial to
led
- LED显示功能，使用VHDL语言编程，基于FPGA-LED display, the use of VHDL language programming, based on FPGA
mux21a
- 2选1多路选择器的VHDL完整描述，即可以直接综合出实现相应功能的逻辑电路及其功能器件。图6-1是此描述对应的逻辑图或者器件图-2 election more than one MUX complete descr iption of the VHDL, which can be directly integrated to achieve the corresponding function logic devices and their functions. Figure 6-1 is th
timer
- VHDL语言设计的数字钟 具有时分秒三段显示-VHDL language designed with time-accurate digital clock shows three paragraphs
VHDL
- vhdl学习总结的文章，初学者建议多看看哦。-VHDL study summed up the article, recommends beginners take a look at multi-Oh.
ethernet_example
- FPGA上实现以太网 用VHDL实现，欢迎多交流 -FPGA to achieve the realization of Ethernet using VHDL welcome more exchanges
VHDL
- 有关VHDL编程的大量例子，很实用的，自动饮料机，电话计费卡等等，很多。-VHDL programming on the large number of examples, very practical, automatic beverage machine, telephone billing card, etc., many.
VHDL_DMF
- Vhdl实现扩频通信匹配滤波器，书上打下来的,打了好久.-VHDL realization of spread spectrum communication matched filter, books, playing down, playing for a long time.
VHDL
- VHDL基础的编程源代码，对初学者很有参考价值-VHDL-based programming source code, useful reference for beginners
write_rd
- 关于VHDL的 关于DSP的 emif-On VHDL on the DSP s EMIF