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clock
- vhdl实现时钟和闹钟功能，此外还可以显示星期几，闹钟可以设置闹铃时间和报时。-implementation vhdl alarm clock and also can show a few weeks, you can set the alarm time and alarm time.
CLK_DIV
- 爱用硬件描述语言VHDL实现输入时钟10分频输出-divide CLOCK by 10 using VHDL
asynFifo
- 异步fifo在IC设计中，非常重要；是异步时钟域同步方法-Asynchronous fifo in IC design, is very important are asynchronous clock domain synchronization
fpga.fifo
- 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the
ADC0809VHDL
- 文件名：ADC0809.vhd功能：基于VHDL语言，实现对ADC0809简单控制说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Descr ipt
shizhong
- 数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on
spi_op_core
- SPI协议的Verilog编程，包括时钟的产生模块，控制模块等-Verilog programming SPI protocol, including the selection of the clock module, control module, etc.
zhushaoyong
- 设计并制作一个14键单音电子琴预先存入一些曲谱电路在4Hz的时钟控制下自动播放 通过220V电源适配器给电路提供工作电源-Design and production of a 14-key electric piano tone into a number of music scores advance in 4Hz clock circuit under the control of automatic play through 220V power adapter to provide
Time
- 24小时时钟设计程序，含有时，分，秒的电路设计，基于VHDL语言，用Quartus 2程序实现。-24-hour clock design process, with hour, minute, second circuit design, based on the VHDL language, using Quartus 2 program.
clock
- 60进制计数器，采用十分简便的方法，能够很快速的完成计数功能。-60 M-ary counter, using a very simple way to very quickly complete the count function.
e3
- 4位可逆计数器：将50MHz的时钟进行 分频后的结果作为时钟控制，根据输入进行条件判断，再通过设置一个四位的向量将结果输出，利用数码管显示在实验板上-CNTR 4: will be conducted at 50MHz clock frequency as the clock after the control conditions to determine the basis of inputs, and then set up a four through the results of th
liuVHDL
- 一种基于状态机设计的串并行转换电路，将LTC1196(ADC)的串行输出数据转换成并行数据的转换电路， ADC的时钟由转换电路提供，-Design a state machine based on parallel conversion circuit of the series will be LTC1196 (ADC) output of the serial data into parallel data conversion circuit, ADC clock provided by
EDAtest
- 关于数字钟的实现，用VHDL实现时，分，秒，的显示，并能报时-Digital clock on the realization of VHDL to achieve with hour, minute, seconds display, and time
8caideng
- 试设计一种彩灯控制器控制8盏灯。该彩灯控制器有4种自动切换的花样。第一种花样为彩灯从右到左，然后从左到右逐次点亮，全灭全亮；第二种花样为彩灯两边同时亮一个逐次向中间移动再散开；第三种花样为彩灯两边同时亮两个逐次向中间移动再散开；第四种花样为彩灯两边同时亮三个，然后四亮四灭，四灭四亮，最后一灭一亮。四个花样自动变换，重复以上过程。输入时钟频率为500Hz，灯亮的时间在1—4秒之间，可以自由控制。电路中以“1”代表灯亮，以“0”代表灯灭。-Lantern try to design a contro
adaptive_lms_equalizer_latest.tar
- In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random.
sdram_vhdl_lattice
- sdram的控制程序，程序分为控制端口模块、时钟模块、数据传输模块及刷新等模块-sdram control procedures, process control port is divided into modules, clock modules, data transfer module and refresh modules
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is desi
shifter
- 移位运算器SHIFTER 使用Verilog HDL 语言编写，其输入输出端分别与键盘/显示器LED 连接。移位运算器是时序电路，在J钟信号到来时状态产生变化， CLK 为其时钟脉冲。由S0、S1 、M 控制移位运算的功能状态，具有数据装入、数据保持、循环右移、带进位循环右移，循环左移、带进位循环左移等功能。 CLK 是时钟脉冲输入，通过键5 产生高低电平M 控制工作模式， M=l 时带进位循环移位，由键8 控制CO 为允许带进位移位输入，由键7 控制:S 控制移位模式0-3 ，由键6 控制
sheji2
- 一个秒表的硬件设计，学习数字电路中基本RS触发器、单稳态触发器、时钟发生器及计数、译码显示等单元电路的综合应用。-The hardware design of a stopwatch, learn basic digital circuit in the RS flip-flops, monostable multivibrator, the clock generator and counting, decoding display unit integrated circuit applic
shizhong
- 时钟程序设计，为用vhdl语言设计编写的电子时钟显示分秒位-Clock programming, vhdl language designed for use in the preparation of accurate digital electronic clock display