搜索资源列表
ADPLL
- verilog ADPLL file with testbench.v
simplevhdl
- 我是VHDL的初学者，这是我自己编译的简单的几个VHDL码，功能有3-8解码器及其testbench,16位寄存器及其testbench和交通灯。 希望能和其他初学者一起讨论学习，并得到高手的指点-I VHDL beginners, this is my own translation of a few simple VHDL code. 3 -8 function decoder and testbench, 16 Register and testbench and traffic li
usb11_systemc
- USB 1.1 PHY的代码，systemc语言 USB 1.1 PHY的代码，systemc语言,包括基于systemc语言的testbench ，和相关的doc文档-USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including systemc based testbench language, doc and related documents
usb1_funct
- usb1.1的verilog源代码。以及其测试仿真文件，现在很难找其测试文件既testbench-usb1.1 verilog the source code. Simulation and test document, and now it is very difficult to find the paper test testbench
16bit_booth_multiplier_STG
- verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-mo
hdb3_verilog
- modelsim工程，用verilog实现的HDB3编码，以及测试程序testbench-modelsim works with verilog realized HDB3 coding, and testing procedures testbench
ModelSim_TestBench_VHDL
- ModelSim TestBench的VHDL模版-ModelSim VHDL template TestBench
VerilogHDLTestBenchPrimer
- 讲解Verilog 的testbench的书写方法。-on Verilog testbench writing.
i2c_slave_con
- 可以支持连续读写的i2cslave源码，很适合作为master的testbench来用-can support continuous reading i2cslave source, very suitable as a master to the use of testbench
cfft
- 参数化FFT源代码，点数和位宽可变，内附testbench和说明文档-parameters of the source code FFT, counting and variable bit-enclosing testbench and documentation
RISCMCU
- riscMCU的VHDL实现，内附有modelsim仿真testbench和文档说明-riscMCU VHDL, modelsim containing a simulation testbench and documentation shows
oc8051
- 8051的verilog实现，内附testbench,c语言调试程序-8051 verilog achieve, enclosing testbench, c language debugging procedures
FIFO_v
- FIFO的verilog实现，内附testbench和文档说明-FIFO verilog achieve, enclosing testbench and documentation shows
systemverilog
- systemverilog是新出现的一种高级硬件描述和验证语言，这里给出了一些书和文章还有使用vmm方法开发testbench的例子
s_fifo
- 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench
fifo
- 一个同步FIFO，包括testbench，
core_arm.tar
- vhdl的arm核 包含testbench
booth
- booth乘法器电路，基四实现，附带有testbench
counter
- VHDL计数器的TestBench，适合初学者
dac
- DAC converter design with Verilog code and testbench