搜索资源列表
VHDL-status
- VHDL状态机学习笔记,对初学者有很重要的帮助意义-VHDL state machine learning notes for beginners has a very important significance help
uart_Transmitter
- 自己写的一个uart驱动代码，是一个工程文件，适合初学者，里面的状态机的写法十分值得学习-To write a uart driver code, is a project file, suitable for beginners, which the wording of the state machine is worth learning
paobiao
- 基于Verilog HDL的完整数字跑表工程，在试验机台上运行验证通过了的。 用8位7段数码管分别显示微妙，秒，分。 有开始，暂停，复位功能。 学习VerilogHDL的经典例子，添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube sho
VHDLstudy
- 近期学习程序小结，对初学者比较有帮助，包括：四D触发器：74175 用状态机实现的计数器 简单的12位寄存器 通用寄存器 移位寄存器：74164 带load、clr等功能的寄存器 带三态输出的8位D寄存器：74374等 -Summary of recent learning process, more helpful for beginners, including: four D flip-flop: 74 175 with a simple state machine im
cpldkeyboard
- cpld利用学习机键盘输入数据，并在数码管显示出来，而且数码管显示位置可以选择-cpld use of learning machine keyboard input data and displayed in the digital control and digital display location option
chap5_voter5
- FPGA学习资料-VHDL语言实现的表决器-FPGA-VHDL language learning materials in the voting machine
EDA3
- 实验目的 1．学习一般有限状态机的设计； 2．实现串行序列的设计。 二、设计要求 1． 先设计0111010011011010序列信号发生器； 2． 再设计一个序列信号检测器，若系统检测到串行序列11010则输出为“1”，否则输出为“0”，并对其进行仿真和硬件测试。 -Purpose of the experiment 1. Learning the general design of finite state machine 2. Serial sequence de
FPGA
- 其中包含一些以前学习时写过的各种加法器和HDB3编码，以及状态机的一些题目-Which contains a number of previously written a variety of learning adder and HDB3 encoding, and the state machine of some of the topics
1
- 学习状态机的设计方法，并利用状态机编写程序。-Learning state machine design and use of state machine programming.
SJ_FSM
- 这是有限状态机的学习资料，详细介绍了设计有限状态机的步骤和方法，对想学习数字系统设计的朋友应该有所帮助-This is a finite state machine learning materials, details the steps to design finite state machines and methods for studying digital system design to a friend should help
UART
- 51单片机之间的双机通讯程序，对学习单片机的UART具有很好的参考价值-51 two-machine communication between the microcontroller program for learning microcontroller UART has a good reference value
verilog-course-design
- 两个关于Verilog语言学习的课程设计，有要求、思路和代码，一个是芯片接口设计，一个是智能烧烤机设计-Two on the Verilog language learning course design, requirements, ideas and code, a chip interface design, a smart barbecue machine design
fsm
- FSM状态机例子，可以给初学者参考学习使用-FSM State machine example, can give the reference for beginners learning to use
a-simple-state-machine
- 简易状态机 verilog实现的简单状态机，全工程不错的 典型历程 值得学习入门很好的实验例程-Simple state machine verilog achieve a simple state machine, the typical course of the whole works good deserves learning entry good experimental routines
EDA
- EDA课件中的状态机的学习资料，是PDF格式-The EDA in state machine learning materials, PDF format
moore
- FPGA实现moore状态机，适合新手学习，开发环境Q2-FPGA implementation moore state machine, suitable for novice learning, development environment Q2
serial_number_check
- 序列检测，学习verilog三段式状态机的经典例程，modelsim仿真无误-Sequence Detection, three-state machine learning verilog classic routines, modelsim simulation is correct
status-code
- 基于FPGA的简单状态机程序，非常适合初级菜鸟学习使用入门程序，欢迎大家下载学习-A simple state machine based on FPGA procedures, very suitable for learning to use primary rookie entry procedures, are welcome to download the learning
LAMP-LED
- 使用VHDL语言中的状态机实现了一个多功能的跑马灯，为状态机的学习提供了一个很好的示例-Example using VHDL language state machine implements a versatile marquees for state machine learning provides a good
mingmie-V4.1
- Based on the time delay estimation of power spectrum, Based on piecewise nonlinear weight value Pso algorithm, Machine learning routines.