搜索资源列表
an488_design_example
- 经典基于FPGA的LCD显示器的控制模块-FPGA-based LCD display control module
Ambilight
- This source code is the same project as the Ambilight.
NewFolder2
- Verilog and VHDL programs for sipo buffer,d flip flop etc
avs_export
- the avalon verilog slave sram interface fron be micron
bemicro_lab_ver
- be micron sram file downloaded from altera be-micro
Long_shift_gate_level
- 1. Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock ris
full_adder_code_in_verilog
- full adder in verilog
Accumulator_ADD_SUB_8bit
- Adder/Subtractor for 8-bit (with full interface with FPGA board and pin assignment)
fifo
- this verilog program for sysnchronous FIFO ,this document contains some error using before correct and then use,-this is verilog program for sysnchronous FIFO ,this document contains some error using before correct and then use,
cla
- Carry Look ahead adder
sheji
- 基于Quartus的数字中设计（包含原工程），运行即可使用！-digitalclock
dac_loader
- Hdl code to load some DAC 8412.
xapp265
- High-Speed Data Serialization and Deserialization(840 Mb/s LVDS) for xilinx fpga
FPGA
- FPGA编程课程演示PPT，包括语法入门，语法进阶和实例分析。-FPGA programming course presentation PPT, including Grammar, syntax and examples of advanced analysis.
seg7led
- 点亮7位LED小灯实验 基于hdl语言 有全部管脚锁定等-seven leds based on verilog hdl
103244864FIR_filter_DA_machine
- 简易fir滤波器，采用分布式算法实现，verilog-Simple fir filter using distributed algorithm, verilog
clz
- 对于一串二进制数前置零的计数的Verilog程序-For a string of binary zero count Verilog pre-procedure
bai2
- excercises verilog add two bcd numbers
part6
- run hello on 7-segments led on de2 board using verilog
part4
- d flipflop using verilog