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ser_adder
- 串入串出加法器 verilog 代码 串入串出加法器 verilog 代码-serial adder verilog code serial adder verilog code
Asqare
- 用fpga实现的连连看游戏，功能还不完善，不过可以借鉴。-Realize with FPGA Lianliankan game, function is not perfect, but can be used for reference.
biye
- 基于UDPIP的传输系统，分为发送模块，接受模块，crc模块等。-Is divided into a sending module, a transmission system based on UDPIP accepting module, crc module.
trafficLight_editedversion
- Traffic light problems in verilog code. Consider a controller for traffic at the intersection of a main highway and a country road The traffic signal for the main highway gets highest priority because cars are continuously present on the main hi
codes
- verilog code for traffic light controller and test bench for verification purpose
fifo_module
- verilog 语言写的FIFO历程，可以很好参考。 -The write FIFO verilog language course, a good reference.
song
- liangzuosong display-"liangzuo" song display
fifo
- VHDL 带FIFO的 UART 求大神帮忙修改-VHDL with FIFO UART pursuing big God help modify
nios_hello_PWM
- nios的pwm源程序例程，修改后，测试可用。欢饮大家修改后使用！-it is nios for vrilog fpag,it s can modify to you learing nois!
CPLD_18b20_uart
- 温度传感器采集数据给cpld，然后由串口上传到上位机；编程语言是verilog；-Temperature sensor collected data to the the cpld, then uploaded to the host computer by serial programming language verilog
RESPONDER
- 上电后蜂鸣器响一声后开始倒计时，抢答后数码管显示抢答结果，倒计时停止。在40秒内若无任何键按下，蜂鸣器长响，结束，LED开始闪烁-The buzzer sounds after power-start countdown digital display Responder Responder results, the countdown stops. If there is no any key within 40 seconds press, long loud buzzer, ending
UART
- 上电后数码管显示：0000，同时串口超级终端软件显示：“=======Ready=======”, 在串口超级终端的窗口输入：0 ~ 9,就可观察-The digital display on power: 0000, while serial HyperTerminal software displays: " the ======= Ready ======= serial HyperTerminal window, enter: 0 to 9, and can be observe
REFRESH
- VERILOG实现数码管动态刷新，开机复位后显示1234-VERILOG digital dynamic refresh, power-on reset is displayed after 1234
I2C
- 基于hdl的i2c开发学习资料，仅供参考，但是对初学者有用。-Based on the the hdl i2c development learning materials for reference only, but is useful for beginners.
8-channel-FIR
- b channel FIR filter verilog
Serialtoparaller
- 序列平行轉換器,對輸入的資料流進行轉換功用-Serial parallel converter to convert the input data stream function
top_hc595
- using FPGA to operate array led of 16x16-using FPGA to operate array led
carrylook4bit
- carry 4-bit adder program in verilog
verilog-hdl
- 王金明：《Verilog HDL 程序设计教程》，包括Verilog HDL的程序，对于初学者有一定的帮助-Wang Jinming: Verilog HDL programming tutorial, including Verilog HDL program, help for beginners
codlab-17-2-12
- Verilog programs- multiplexer, encoder etc