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嵌入式应用技术基础教程1
- 嵌入式应用技术基础教程1 第1章 嵌入式应用技术概述 第2章 嵌入式应用技术的硬件基础 第3章 高级语言的串行通信编程 第4章 Freescale 08系列单片机概述 第5章 HC08 CPU与汇编基础 第6章 通用I/O与第一个汇编程序 第7章 08C语言 第8章 串行通信接口SCI与串行外设接口SPI 第9章 键盘中断模块与A/D转换模块 第10章 定时接口模块-embedded applications guide a technical basis
Dqiangdaqi
- 它由主体电路和扩展电路两部分组成。主体电路完成基本的抢答功能，即开始抢答后，当选手按动抢答键时，能显示选手的编号，同时能封锁输入电路，禁止其它选手抢答。扩展电路完成定时抢答的功能。 -it from the main circuit and the circuit extended two components. The main circuit completed basic Responder function, which is to begin Responder, when activ
8031motor
- 给出了8031控制步进电机的时序图，并给出了相应的代码供参考。-given the 8031 stepper motor control the timing map and the corresponding code for reference.
ISE-TIMING-analyse-for-chinese-
- ISE在时序约束时详细步骤.针对高速时钟下的时序不满足时的设计.-ISE timing constraint in the detailed steps.
DVI_timing
- DVI的时序说明，有了这个，才能开发DVI显示接口，没有这个寸步难行-DVI timing instructions, with this in order to develop DVI display interface, without this move an inch
DDR
- 关于DDR SDRAM的详细原理和时序分析,对于开发设计有很大使用价值-DDR SDRAM on detailed principles and timing analysis, design for the development of a great value
Ashort-timeFouriertransformbasedsymboltimingaproac
- A short-time Fourier transform based symbol timing approach for OFDM systems
VX1828BBrief
- timing lcd controller
lcdtimingcontrollervx1828
- lcd timing controller
0909.0573
- this a paper on minimizing cache timing attack on aes using cache flushing algorithm-this is a paper on minimizing cache timing attack on aes using cache flushing algorithm
LTE_transmition_technoiques
- 分析了LTE系统频率偏移，定时误差，信道估计问题等，并对广义Rake接收机和CPEDS接收机的性能做了比较。-Analysis of the LTE system frequency offset, timing error, channel estimation problems, and generalized Rake receiver performance receiver and CPEDS were compared.
Freq-and-timing-recovery
- 文章介绍了平坦衰落下的频偏和同步联合恢复技术，能够有效应对时变的信道，并且不需要训练序列，给出了详细的仿真和分析，供大家学习-Two open-loop algorithms are developed for esti- mating jointly frequency offset and symbol timing of a linearly modulated waveform transmitted through a frequency-fl at fading
How-to-read-timing-diagram
- 时序 ，就是按照一定的时间顺序给出信号 就能得到你想要的数据，或者把你要写的数据写进芯片 -Timing Timing is given by a certain time sequence signal can get the data you want, or you write the data written into the chip
Matched-filtering-and-timing-recovery-in-digital-
- Matched filtering and timing recovery in digital receivers 0901Litwin32
LabView-software-timing
- LabView中软件定时程序设计，包括介绍C++包如何使用。-LabView software timing in programming
VerilogHDL-for-timing-design
- 这是一本关于如何进行硬件时序设计的文档，对时序设计困难的朋友很有帮助 VerilogHDL时序篇.pdf-This ebook is about the timing design in FPGA, very helpful
Interpreting-the-Timing-Diagram
- 对The 68000 Read Cycle时序的分析-Interpreting the Timing Diagram to the 68000,A 68000 memory access takes a minimum of eight clock states numbered from clock state S0 to clock state S7
how-to-read-the-timing-diagram
- 一份让你知道如何看懂众多芯片时序图的好资料-Let you know how to read a timing diagram of good information
TimeQuest-Timing-Analyzer
- TimeQuest Timing Analyzer
altera-timing
- Altera时序分析基础，帮助提升时序分析能力，建立时序分析模型。-The base of Altera timing analysis.