搜索资源列表
shixv
- 时序控制器程序，51汇编，作用：分时接通/断开各路加热板（有24路），防止大电流对电网过冲击。-Timing controller procedures, 51 compilations, role: Time to connect/disconnect the various heating plate (24 Road), to prevent high-current-off impact on the power grid.
shiyanbaogao
- 实验报告 计算机组成原理 启停、时序电路实验-Principles of Computer Organization experimental report start and stop, timing circuit experiment
Timing_Closure_Cadence
- Cadence的关于Timing Closure（时序收敛）的ppt-Cadence s ppt for Timing Closure
frequencymeter
- 数字频率计课程设计 描述计时功能等功能-Digital frequency meter function of curriculum design, timing and other functions described in
Advanced-Xilinx-FPGA
- Advanced Xilinx FPGA Design with ISE Objectives Describe Virtex™ -II advanced architectural features and how they can be used to improve performance • Create and integrate cores into your design flow using the CORE Generator™
j3
- 用Javascr ipt实现图片的定时更换-Using Javascr ipt to replace the timing to achieve picture
CadenceTimingAnalysis
- 使用Cadence进行PCB时序分析好文章，对于学习SI仿真有很大的用处。文章很实用。-Cadence timing analysis a good article, for the rest SI simulation is very useful. Very useful article
eee
- 基于OFDM的定时和频偏估计的联合算法，-OFDM-based joint timing and frequency offset estimation algorithm
Trafficcontrolsystemdesign
- ⒈ 了解交通灯管理的基本工作原理 ⒉ 熟悉8259中断控制器的工作原理和应用编程 ⒊ 熟悉8255并行接口的各种工作方式和应用 ⒋ 熟悉8253计数器/定时器的工作方式及应用编程，掌握利用软硬件相结 合定时的方法 ⒌ 掌握多位LED显示问题的解决 -But understand the basic principle of management of traffic The 8259 interrupt controller with the working princi
FPGA-Timing-Function-Model-Analysis_1
- IR Drop Analysis and Timing-Function Model Generation for Embedded FPGA(I).
FPGA-Timing-Function-Model-Analysis_3
- IR Drop Analysis and Timing-Function Model Generation for Embedded FPGA(III).
tcd1209d
- 根据 TCD1209D 的结构及工作原理，我们知道驱动时序的准确性决定了 TCD1209D 输出信号的性能。本课题中设计的 TCD1209D 驱动时序，典型稳定工 作频率为 1MHz ，最高工作频率为 10MHz。 -According to TCD1209D the structure and working principle, we know the accuracy of timing-driven TCD1209D output signal determines the
ADS1259
- 24位ADC ADS1259技术手册，详细的功能和特性说明，寄存器时序操作，还有电路解说-24-bit ADC ADS1259 technical manuals, detailed descr iption of functions and features, register timing operation circuit explanation
about-spi
- 主要讲的的spi的相关概念和spi的时序问题，不懂spi的可以-Mainly about the spi spi-related concepts and issues of timing, do not know can see spi
verilog-ieee.pdf.tar
- IEEE 2001 verilog 标准 ,详细讲述了 业内 公认的 VERILOG 标准 ,-The Verilog¤ Hardware Descr iption Language (Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstractio
T315XW01-V5
- T315XW01-V5规格书。包括各个引脚的功能说明。时序图等-T315XW01-V5 specifications. Including the descr iption of the function of each pin. Timing diagrams
pptClcok
- ppt中使用自动计时功能实现。时钟美观，自动提示演说者。-ppt achieved in the use of automatic timing function. Beautiful clock, automatically prompts speaker.
2gbddr2
- DDR2数据手册 描述DDR2 SDRAM数据访问时序-DDR2 Data Manual, describes the DDR2 SDRAM data access timing
DMTv1r12D3
- 各种电视信号的国际标准，包括NTSC， PAL， 1080I ， VGA，XVGA等。有详细的时序说明。-VESA and Industry Standards and Guidelines for Computer Display Monitor Timing (DMT)
Timing-Analyzer-Guide-3.1i
- Timing analyser for xilinx