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seq_div
- 除法器设计 样例程序-Divider design sample program
(19)
- 在7段数码管上显示4个数字（9527）可以更改-In the 7-segment digital display 4 digit (9527) can be changed
AVALON_PWM_B
- L利用verilog编写的PWM代码，易于理解-L using the PWM verilog code written and easy to understand
PLL_100M
- 实现pll分频功能倍频功能可得到fpga说需要的频率实现多的时钟输入-Multiplier pll divide function to achieve functionality available fpga said I need to achieve multi-frequency clock input
traffic
- 利用状态机编写的交通灯,东西南北两条街区，分别采用红黄绿灯-traffic light
tlc5620dac
- 实现数字信号到模拟信号的转换功能，可用电压表测得电压与数字信号对比-Digital signal to analog signal conversion functions available voltage meter measured voltage and the digital signal contrast
xapp882
- This application note describes the implementation of SERDES Framer Interface Level 5 (SFI-5) [Ref 1] in a Virtex-6 XC6VLX240T FPGA. SFI-5 is a standard defined by the Optical Internetworking Forum (OIF). The interface must operate bidirectionall
FFTPVerilog
- FFT Verilog RTL 经过测试与Altera FFT IP相当-FFT Verilog RTL Altera FFT IP
SPI20130811
- 实现高速的数据采集的SPI通信（和M3）-Achieve high-speed data acquisition
XIlinxISELinces
- XilinxISE破解说明及其重要的Linces-Absolutely genuine crack the key
fenpin_clk
- FPGA的分频设计，使用spartan 3e开发板50Mhz频率，包含LED灯环节-Divide the FPGA design, use spartan 3e development board 50Mhz frequency, including LED lights links
VGA1
- spartan 3e开发板平台VGA显示（多条纹路分段），FPGA使用verilog语言设计-spartan 3e development board platform VGA display (multi-stripe road segments), using verilog language design
crc32
- crc-32 主要用于网络传输中的 检测，防止错误数据传输-verilog hdl
AD7689_Avalon_core
- ad7869 FPGA驱动程序 采用verilog 编写-ad7869 FPGA verilog code
verilog_hdlqudou
- verilog_hdl按键去抖动算法模块-verilog_hdl button debounce algorithm module
Module_ReadSRAM
- This an sample to read data from SRAM in FPGA DE2-This is an sample to read data from SRAM in FPGA DE2
key_duli
- FPGA实现verilog语言的按键防抖功能，能够很有效的实现了按键的加减数据的功能，通过一位数码管显示。-FPGA implementation verilog language button image stabilization feature, can be very effective to achieve the subtraction key data features, through a digital display.
src
- Concatenator for calculator synthesizable in verilog hdl.-Concatenator for calculator synthesizable in verilog hdl.
Key2VGA
- PS2 Keyboard to VGA demo for FPGA
vga_block2
- 一个xilinx工程，自己做的，主要是在VGA上显示一个动态方块，在屏幕上自由移动，碰壁反弹-A xilinx project, do it yourself, is mainly a dynamic display box on the VGA, freedom of movement on the screen, snags a rebound