搜索资源列表
ht_fifo
- fifo 读写代码,能够进行速率匹配,很好的源代码-verilog hdl
20131010-code
- fx2lp 68013 xilinx XC3s400 实现slave fifo通讯,包括68013的固件以及fpga的代码(verilog)。摸了好久才调试通过的,特共享出来解救苍生!-fx2lp 68013 xilinx XC3s400 slave fifo
uart_fifo
- 带fifo的串口通信verilog设计,该设计为学习uart所用,完成PC端发送至fpga后fpga原数据返回,支持长字符串。-Serial communication with fifo verilog design, which is used to learn uart complete PC sends data back to the original post fpga fpga, support long strings.
synchoronous_FIFO(jianban)
- 基于IPcore的同步FIFO的设计。采用Verilog代码书写。读写位宽均为8bit,深度为32.-IPcore synchronous FIFO-based design. Using Verilog code writing. Read and write bits wide are 8bit, depth is 32.
FIFO64
- FIFO级联,利用verilog语言实现Xilinx FIFO18单元的多个级联,增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
fifo_datapath
- verilog实现,串转并通过fifo再并转串,可以满足输入速率自由输出的一半时,输出仍可持续发送-verilog achieved, and through serial switch and switch again fifo Series, Rate free importation to meet half of the output, the output is still sustainable Send
vga_pannel_design
- verilog代码写的控制vga显示的实例,利用状态机进行描述,很好的参考例子-verilog language write serial fifo instance, because the serial port speed is relatively slow, a lot of the interface will use fifo buffer
I2S
- 本代码提供一种音频I2S读取数据的verilog代码,并且向fifo写入-This code provides an I2S audio data is read verilog code, and write to the fifo
fifo2
- 异步fifo 先进先出 用于缓冲数据,用verilog HDL所写,在quartus II中测试通过,modelsim仿真-Asynchronous fifo FIFO for buffering data, using verilog HDL written in quartus II test through, modelsim simulation
asyn_fifo
- 本文同步FIFO为TPRAM(两端口RAM,一读一写)。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by
FIFO64
- FIFO级联,利用verilog语言实现Xilinx FIFO18单元的多个级联,增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
fifo_datapath
- verilog实现,串转并通过fifo再并转串,可以满足输入速率自由输出的一半时,输出仍可持续发送-verilog achieved, and through serial switch and switch again fifo Series, Rate free importation to meet half of the output, the output is still sustainable Send
SRAM_WR
- 本人自己经过实践检验的SRAM读写器,用Verilog编写的,可以作为FIFO使用。-I own proven SRAM reader, using Verilog prepared, can be used as a FIFO.
New_UART_verilog
- 这个是最新的UART的verilog代码,里边含有和UART相关的所有function,比如状态机,接收发送FIFO等相关代码。-New UART verilog sample code,Include FIFO code state mashine code ,recevier/trasmiter code
FT245BL_test
- (1)FT245BL芯片datasheet(2)test,USB 转FIFO 芯片测试的verilog程序-(1) FT245BL chip datasheet (2) test, USB transfer FIFO chip testing procedures verilog
syn_fifo_style_1
- verilog实现的,异步FIFO。所有代码在一个模块中。-verilog achieve, asynchronous FIFO. All code in a module.
fifo_verilog
- 16位FIFO的硬件电路,使用verilog实现。文件内含组合逻辑和寄存逻辑两种方法的实现,以及对应的testbench测试代码-16 FIFO hardware circuits using verilog implementation. File contains a combination of logic and storage logic to achieve the two methods, and the corresponding testbench test code
asyn_fifo
- verilog asyn_fifo,内含详细说明,同步FIFO为TPRAM-asyn_fifo include detailed instruction,Synchronous FIFO for TPRAM
syn_fifo
- Verilog,syn_fifo ,内含详细说明,同步FIFO为TPRAM-Verilog, syn_fifo, containing detailed instructions for synchronous FIFO TPRAM
sync_fifo
- 同步fifo实现代码,包括的参数:数据宽度、fifo深度、地址宽度;状态信息包括:full, empty。-verilog RTL code which implement a synchronous FIFO function with data width, fifo depth, address pointer width parameterized.