搜索资源列表
DSP-533M-ddr2RAM4C6455.rar
- C6455 的 533M DDR2 ram 控制程序。完整代码，可以直接使用。,533M DDR2 ram the C6455 control procedures. Integrity of the code, can be used directly.
DDR2LayoutGuide.rar
- DDR2 Module Master Layout Reference Guide2.pdf,DDR2 Module Master Layout Reference Guide2.pdf
smdk2416_rev0_1_cpu_ddr2_080529
- 三星新的ARM9 S3C2416的电路图纸，可支持DDR2,MLC FLASH-Samsung ARM9 S3C2416 new circuit drawings, supports DDR2, MLC FLASH
DDR2_16bit
- ddr2原理图设计，原厂电路图设计，很好很强大 16bit-ddr2 schematic design, the original schematic design, a very powerful 16bit
DDR2_Memory_Test
- DDR2 controller which contains verilog files，pdf and so on
Crack_QII81_FULL_License
- quartus 8.1 ipcore lic,包含ddr、ddr2、fir、nco-quartus 8.1 ipcore lic, with ddr, ddr2, fir, nco
Spartan6_DDR2-
- Spartan6 硬核MCB读写DDR2 实战篇-Spartan6 real hard-core DDR2 MCB articles to read and write
ddr_ddr2_sdram9.0
- altera 公司提供的ddr_ddr2_sdram9.0，DDR2 SDRAM 源代码-altera provided ddr_ddr2_sdram9.0, DDR2 SDRAM source code
DDR_Eye_Patterns
- DDR1 DDR2 DDR3眼图分析。本文根据自己设计的DDR“读”“写”分离软件，介绍一种把“读”眼图和“写”眼 图分离开的方法，并创新地引入模板测试的方法。-DDR1 DDR2 DDR3 Eye Patterns
X900_Z228_spec
- jade x900 z228 specification（include：arm926，ddr2，h264 decoder,mpeg4 codec, lcd&tv encoder）
byNeyno_
- micron data sheet for designing the ddr2 sdram controller part1
DDR2_ctrl
- DDR2 SDRAM控制器的设计及FPGA验证
c4gx_f896_host_ddr2a_odt
- ALTERA PCIE FPGA开发板（EP4C平台）DDR2内存测试代码-ALTERA PCIE FPGA development board (EP4C platform) DDR2 memory test code
DDR2Controller
- DDR2 Controller DDR2 Controller
ddr2sdram_spartan3s700an.tar
- It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit - Diligent fully working.-It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Sparta
modelsim_ddr2sdram_spartan3s700an.tar
- Modelsim DDR2 SDRAM files
DaVinci_EVM_testHardware
- TI达芬奇dm644x各硬件模块测试代码，包括nor flash、nand flsh、ddr2 ram、video loop back等。-TI davinci dm644x hardware test source code，include nor flash、nand flsh、ddr2 ram、video loop back and so on.
Micron_DDR
- DDR2 SDRAM 颗粒初始化以及读写操作时序-Particles as well as the DDR2 SDRAM initialization timing to read and write operations
ddr2_device_operation_timing_diagram_may_07_1
- DDR2时序规范，DDR· DDR2时序规范，DDR·-DDR2 timing norms, DDR DDR2 timing norms, DDR
Xil3SD1800A_MIG_simplifiedUI_vlog_v92
- verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller