搜索资源列表
HDLC
- verilog HDL语言编写的HDLC协议的IP核，包括通讯控制及CRC。-written in verilog HDL HDLC protocol IP core, including communications control and CRC.
iir
- 基于verilog HDL的IIR数字滤波器的实现-Verilog HDL-based implementation of the IIR digital filter
X-HDL3.2.52
- vhdl和Verilog HDL相互转换的软件，很难找的一款-vhdl and Verilog HDL mutual conversion software, very difficult to find a
ds18b20
- 单路DS18B20的verilog HDL 代码，精度为1℃无须转换数据，直接输出结果。占用300个LE资源。-Single DS18B20 the verilog HDL code, and an accuracy of 1 ℃ without converting the data, direct output. Occupy 300 LE resources.
ping_pong_buffer
- 用寄存器来实现乒乓缓存(Verilog HDL)-Ping-pong with the register to achieve cache (Verilog HDL)
lfsr
- 伪随机序列产生器－线性反馈移位寄存器，Verilog HDL 原代码。-Pseudo-random sequence generator- linear feedback shift register, Verilog HDL source code.
EEPROMVerilog-HDL
- EEPROM的Verilog HDL源代码，代码全-EEPROM of the Verilog HDL source code, code all. . . . . . . .
mcst
- 曼彻斯特编码实现，verilog HDL 做的，我也是从网上下的-Manchester encoding to achieve, verilog HDL to do, I am also from the Internet under
I2C
- 用verilog HDL实现I2C Master Controller 的设计，包括主程序设计和测试程序设计-Verilog HDL using I2C Master Controller to achieve the design, including the main program design and test program design
multiply
- Verilog hdl语言 常用乘法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used multiplier design, can use the ModelSim simulation
1602
- verilog HDL语言编写的完整工程，功能是点亮1602lcd，在lcd上显示英文和数字-verilog HDL languages complete works, the functions of light 1602lcd, in the lcd display in English and the number of
spi_verilog
- SPI协议Verilog HDL程序，内含testbench 文件
Verilog
- FPGA经典例子，可以让大家更好的学习Verilog HDL-Classic example of FPGA, allowing you to better learn Verilog HDL
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
decoder
- 指令译码器的设计vhdl语言或者verilog HDL语言对单片机程序的处理-Instruction decoder design vhdl language or verilog HDL language processing microcomputer programs
fir
- 利用FPGA中verlog HDL实现FIR滤波功能,可自行设置相关参数，生成模块-Verlog HDL in the use of FPGA realization of FIR filtering, the provision of the relevant parameters can generate module
Altera-Recommended-HDL-Coding-Style
- Altera 推荐的HDL编码风格，在学习HDL的时候比较重要，另外对HDL到RTL的映射有一定的帮助。-Altera Recommended HDL Coding Style
Verilog.HDL.Experiment
- Verilog.HDL.Experiment.例程-Verilog.HDL.Experiment. Routine
HDB3
- 用Verilog HDL语言进行HDB3编码，并通过Quartus Ⅱ仿真验证-With the Verilog HDL language HDB3 coding, and simulation by Quartus Ⅱ
source3-6
- verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，3-6章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 3-6