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LCD
- lcd verilog hdl 源码 可以直接使用，适用modelsim-lcd verilog HDL source
FPGA
- VHDL、Verilog HDL语言，是华为公司的技术指导书，希望对你有所帮助-VHDL、Verilog HDL
Verilog_Digital_Design_Synthesis
- Verilog HDL A guide to Digital Design and Synthesis Samir Palnitkar SunSoft Press 1996
verilog
- 通过I2C接口读写EEPROM 在本项目中，我们利用Verilog HDL实现了部分I2C总线功能，并能够通过该总线对AT24C02进行读写操作。为了便于观察读写eeprom的结果，我们将读写的数据同时显示在七段数码管上，并设定读写的数据从0到255不断循环，这样就可以方便进行比较。 -Through the I2C interface to read and write EEPROM in this project, we use Verilog HDL to achieve some o
clock
- verilog HDL 编写的时钟分频器-prepared by the clock divider verilog HDL
Guide_to_HDL_Coding_Styles_for_Synthesis
- 讲述了HDL编码风格的一本好书，不论使用VHDL或verilog的都可以-HDL coding style tells a good book, regardless of the use of VHDL or verilog can take a look at the
i2c
- verilog hdl file i2c interfacing-verilog hdl file i2c interfacing
Chapter11-13
- 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个
usartverilogydm
- verilog hdl在FPGA设计中广泛应用，好的程序代码是学习verilog的好帮手-verilog hdl widely used in the FPGA design, a good code is a good helper to learn verilog
clock
- 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings.
cpu_16bit
- design cpu 16 bits by verilog HDL.
Processor_alu
- this Code is in verilog HDL. This Code is for piplined processor with 4 opcode. this will work in three cycle latch, decode and exicute.. test bench for xilinx ise is laos given
AutoWashing
- 基于verilog-hdl的洗衣机自动控制电路，经下载仿真测试通过 附带时钟分频器-Verilog-hdl-based automatic control circuit of the washing machine, after download the simulation test
hdlcodermimo
- hdl coder mimo hdl coder mimo hdl coder mimo-hdl coder mimo hdl coder mimo hdl coder mimo hdl coder mimo
hdlcoderviterbi
- hdl coder viterbi hdl coder viterbi hdl coder viterbi-hdl coder viterbi hdl coder viterbi hdl coder viterbi hdl coder viterbi
SDRAMverilog
- SDRAM 驱动，Verilog HDL源码-SDRAM-driven, Verilog HDL source code
linkMQ
- 一个简单介绍如何使用Matlab生成HDL代码，如何让使用Matlab和Modlsim联合仿真-A brief introduction how to use the Matlab generated HDL code, and how to make co-simulation using Matlab and the Modlsim
Verilog-DRAM
- fpga(veriloh hdl)编写的SDRAM程序说明 -fpga(veriloh hdl)SDRAM
finalcoursework
- 用VHDL代码写的模拟微处理器核程序，有计算模块和register file 等模块，并包含测试程序，调试程序 ACTIVE HDL-Simulation with the VHDL code is written in the microprocessor core procedures, such as computing modules, and register file module, and includes test program, the debugger ACTIVE HDL
Verilog-HDL
- 《北航常晓明Verilog应用》一书的pdf完整版，是学习Verilog的好书-" Beihang Chang Xiaoming Verilog Applications" pdf full version of the book is a good book to learn Verilog