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divide
- Verilog hdl语言的常用除法器设计，可使用modelsim进行仿真-Commonly used languages Verilog hdl divider design, can use the ModelSim simulation
husw
- 用VHDL语言设计维特比 解码器 是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
uart2fli
- Modelsim FLI接口设计实例，适合学习Modelsim fli接口编程者学习。-Modelsim FLI interface design for learning Modelsim fli learn programming interface.
modelsim_se_tut
- MODELsim公司的使用手册，新手适用。详细讲解了仿真方法步骤-ModelSim s user manual applies to novice. Explain in detail the simulation method steps
matlab_modelsim
- Matlab 与 modelsim 协同仿真的例程设置好modelsim运行环境后，在源码路径执行manchester_tb，即可完成协同仿真的过程。-ModelSim co-simulation with Matlab routine ModelSim runtime environment is set up after the implementation of source path manchester_tb, to complete the process of co-simulat
ModelSim_example
- modelsim仿真流程，附有两个源码（vhdl),做设计例子，按步骤操作并添加源码，即可看到仿真波形输出-ModelSim simulation process, with the two source code (vhdl), to do a design example, according to these steps and add the source, you can see the simulation waveform output
XiaYuWen_8_RISC_CPU
- 夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试） modelsim工程文件，包括书中所测试的三个程序和相关数据，绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的，只有一个mcu的代码，但很多和书中的是不一样的，自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方，如clk_gen.v中clk2,clk4是没有用的，assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的，会使时序恶
FIFO
- it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a
clock
- 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 多功能数字钟-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock
sell
- 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 自动售饮机 电话计费器程序-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Drink vending machine telephone billing program
yuelao
- 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 用VHDL语言仿真歌曲刘德华的《月老》-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Using VHDL simulation language song Andy Lau' s " 月老"
QuartusIIandModelSim
- 本文主要描述了如何在QUARTUS II 中输入程序文件，生成网表及标准延时文件，然后通过 MODELSIM进行功能仿真与后仿真的过程，主要为图解，含全部代码及仿真波形。 -This article describes how to enter at QUARTUS II program file, generate netlists and standard delay file, and then through the ModelSim for functional simulation
modelsim
- modelsim入门，简单易学，容易上手。丰富说明-modelsim entry, easy to learn, easy to use. Note the rich
Quartus7.2andModelSim
- 结合截图，quartus2与ModelSim的联调的详细操作步凑，使初学者迅速上手-Combination of shots, quartus2 with the ModelSim FBI put together a detailed step-by-step operation, so that beginners get started quickly
source
- ModelSim对Altera设计进行功能仿真的简单操作步骤-modelsim simulation
CPU
- Xilinx Modelsim下制作的处理器设计以及添加了外部接口处理。-Xilinx Modelsim produced the design of the processor, and add an external interface.
fpga_DO
- 根据ModelSim提供的命令或者Tcl/Tk语言的语法，将仿真Cmd流程的仿真命令依次编写到扩展名为“do”的宏文件中，然后直接执行这个DO文件，就可以完成整个仿真流程-According to the order provides ModelSim or Tcl/Tk language syntax, the simulation process simulation Cmd command followed by the preparation of the extension "
Modelsim_Advanced
- 介绍modelsim的使用说明，文字浅显易懂-modelsim user guide
Desktop
- it is the ps2 interface code writed in modelsim
MODELSIM
- Modelsim 经典教程，推荐大家看下-Modelsim Tutorial classic recommend you facie