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Carrier & Symbol Timing Recovery
- Carrier & Symbol Timing Recovery-Carrier Symbol Timing Recovery
Timing
- Timing execution time can write their own,Let us study it slowly huh
VESA-Monitor-Timing-Standard
- VESA monitor timing standard
VGA Output
- VGA Timing Output display
graph, heap, sorting, timing source code-- common datastruct
- graph, heap, sorting, timing source code
graph, heap, sorting, timing source code-- common datastruct
- graph, heap, sorting, timing source code
VESA_Timing_2004.rar
- VESA标准Timing_2004,包括当时所有VESA信号的标准，对于视频开发人员十分重要的参考资料,VESA standard Timing,2004. This document includes all current VESA Monitor Timing Standards & Guidelines.It is very important for Video Developer.
ISE-TIMING-analyse-for-chinese-
- ISE在时序约束时详细步骤.针对高速时钟下的时序不满足时的设计.-ISE timing constraint in the detailed steps.
TimingDesigner
- 非常简单易用的画时序图工具，用于时序设计、流程分析很实用-Very easy to use timing diagram drawing tool for timing design, flow analysis is very useful
OFDM_16QAM
- ofdm下的QAM调制解调系统实现，包括定时同步-QAM OFDM modulation and demodulation under the system implementation, including timing synchronization
DVI_timing
- DVI的时序说明，有了这个，才能开发DVI显示接口，没有这个寸步难行-DVI timing instructions, with this in order to develop DVI display interface, without this move an inch
6732448-Basic-Timing-Constraints-Tutorial
- timing constraints in fpga
Timing
- 定时误差估计，精度很高，算法简单易于实现，很值得参考！-Timing error estimates, precision is high, the algorithm simple and easy to implement, it is worth considering!
timing
- timing recovery using squaring method
timing
- sc-fde（单载波频域均衡）系统的定时功能仿真-sc-fde (single carrier frequency domain equalization) system timing functional simulation
VGA-timing
- VGA 图像时序分析，是VGA测试的入门资料-VGA timing, very good for study VGA
How-to-read-timing-diagram
- 时序 ，就是按照一定的时间顺序给出信号 就能得到你想要的数据，或者把你要写的数据写进芯片 -Timing Timing is given by a certain time sequence signal can get the data you want, or you write the data written into the chip
can-bus-bit-timing-setting
- 在CAN总线中,位定时有一点小错误就会导致总线性能严重下降。虽然在许多情况下，位同步会修补由于位定时设置不当而产生的错误，但不能完全避免出错情况，并且在遇到两个或多个CAN节点同时发送的情况时，错误的采样点会使节点启动错误认可标志，使节点不能赢得总线上的任何活动。因此要分析、解决这样的错误就需要对CAN总线位定时中的位同步和CAN节点的工作过程有一个深入的了解。本文描述了CAN总线位同步的运行规则以及如何对位定时的参数进行设置。-In the CAN bus, there is a little
timing and trace generator for opengl
- Qsilver is a simulation framework for graphics architec- tures that can simulate low-level GPU activity for any exist- ing OpenGL application [10]. Qsilver uses Chromium [7] to intercept and transform an OpenGL application’s API calls and create an a
VESA Timing标准
- 查看标准vesa timing规范，便于显示器产品开发(View the standard VESA timing specification)