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uart16550.tar
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with modem or other external devices, like another computer using a serial cable and RS232 protocol. This core is
uart16550
- uart16550 ＩＰ核 ＨＤＬ源代码，对设计自己uart的人员和学习串口通讯有一定的参考价值！其中，附有详细的所明文档！-uart16550 IP HDL source code, uart to design their own study of serial communication and has some reference value. Which, with detailed documentation as prescribed!
uart_core_vhdlORverilog
- 串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)\\uart 源码 (Verilog)\\uart 源码 (VHDL)\\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice versi
uart16550
- uart source code from opencore
16550
- UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。
uart16550.tar
- UART16550 controller, verilog
uart16550.tar
- uart16550 ip core 通用异步收发器vhdl源代码
uart16550
- uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can b
mini_or1200
- openrisc mini_or1200, 包括 or1200、uart16550、dbg_interface、mem_if(片上内存)这几部分。-openrisc mini_or1200, including or1200, uart16550, dbg_interface, mem_if (memory chip) in these parts.
uart16550
- Ｕａｒｔ 串口的verilog实现已调试通过-verilog
uart_testbench
- opcore.org "uart16550" 项目的testbench-test bench of "uart16550" project
UART16550
- UART控制器，集成FIFO，寄存器，数据位宽8位-UART controller, with FIFO, register, databus 8bits
uart16550
- Implementation of the UART 16550 model with verilog langugue
OpencoresUART16550doc
- UART16550 的开发核的详细说明文档-UART16550 detailed descr iption of the development of nuclear documents
UART16550(Verilog)
- 通过各项仿真的模块代码，是一个标准的模块，可以直接使用-Through various simulation module code is a standard module, can be used directly
uart16550_latest.tar
- UART16550是较为通用的串口协议，压缩包内有4个文件可供选择，直接提供RTL源码，可直接导入到工程内。-Uart16550 core is used for Serial Commuication.There are 4 folders in the zip package and have the verilog RTL which can be added in the project.
uart16550_VERLOG
- 采用VERILOG实现完整的UART16550协议，提供RTL代码、仿真文件-Using VERILOG achieve a complete UART16550 agreement to provide RTL code, simulation files
uart16550.tar
- UART Verilog RTL Code
uart16550_latest.tar
- UART16550是16550兼容的UART核心（主要）。 总线接口是WISHBONE SoC总线启。B. 所有功能的标准选择16550 UART：FIFO的基础操作，要求和其他中断。 数据表可以下载从CVS树随着源代码-uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standa