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renmin331
- FPJA Verilog序列检测器1001 -1001 Sequence Detector
XULIEQI
- 用状态机实现序列检测器的设计 序列检测器可用于检测一组或多组由二进制码组成的脉冲序列信号，当序列检测器连续收到一组串行二进制码后，如果这组码与检测器中预先设置的码相同，则输出a，否则输出b- With a state machine sequence detector design Sequ
Moore-type-sequence-detector
- 基础实验_有限状态机：Moore型序列检测器-Experimental basis _ finite state machine: Moore-type sequence detector
seq_detector
- 3比特的任意二值序列检测器(例如101、110、001等)。从任意序列中检测出三比特的序列。包含VHDL源码以及testbench测试源码程序。-The 3-bit binary sequence of any detector (e.g., 101,110,001, etc.). A three-bit sequence is detected from an arbitrary sequence. Includes VHDL source code and testbench test so
xuliejiance
- 设计一个二值序列检测器，即如果连续检测到1110010序列就输出为1，否则为0。-Design of a binary sequence detector, i.e., if the sequence is continuously detected 1110010 outputs 1, otherwise 0.
Vrilog-hdl--Sequence-check.doc
- 用VrilogHDL编写的一个序列检测器-use rilogHDL define a Sequence check Instrument
checkfor1101
- 1101序列检测器，VHDL编写，外部输入任意序列，一旦检测到1101就亮led提示。-1101 sequence detector, VHDL prepared, external input arbitrary sequence, once detected 1101 bright LED tips.
jc1101
- 用状态机实现序列检测器的设计，了解有限状态机的设计与应用。-With a state machine sequence detector design, understand the design and application of finite state machines.
sequence-detector
- 3比特的任意二值序列检测器，Quartus 10.0+modelsim 6.5SE联仿真报告形式-3 bits of arbitrary binary sequence detector,simulation with Quartus 10.0+ modelsim 6.5SE，report forms
detector-(1110010)
- 序列检测器（1110010）设计 ，Quartus 10.0+modelsim 6.5SE联仿真报告形式-Sequence Detector (1110010) designs, simulation with Quartus 10.0+ modelsim 6.5SE ， reports
xuliejianceqi
- 序列检测器00101，包括源代码，testbench，ise13.4测试以及综合通过等说明文档。-Sequence detector 00101, the state machine verilog, testbench, ise13.4 simulation map. The test is successful
VHDL
- 先设计序列发生器产生序列：1011010001101010；再设计序列检测器，检测序列发生器产生序列，若检测到信号与预置待测信号相同，则输出“1”，否则输出“0”，并且将检测到的信号的显示出来。-First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is dete
The-state-machine
- 状态机实现序列检测器的设计，并对其进行仿真和硬件测试-The state machine implementation, the design of sequential detector and carries on the simulation and hardware test
eight-number
- 八位数据选择器和序列10010检测器，数据选择器具有数据选择功能，序列检测器是一个自动检测序列功能-Eight data selector 10010 and the sequence detector, a data selector having a data selection function, the sequence detector is a sequence of automatic detection function
xuliejiancejisuanqikongzhiqi
- VHDL序列检测器，计算器，控制器编码以及实现方法。-VHDL sequential detector, calculator, controller and its implementation method.
code
- 本源码是基于VHDL语言环境下的基础实验源码，共分七个部分。分别是：序列检测器、数字密码锁、四位有符号数除法、同步FIFO、DPLL的设计以及Cordic 算法实现。对于VHDL的初学者具有极大的参考价值。-The source is based on experimental basis source VHDL language environment, it is divided into seven sections. They are: the sequence detector, di
FSM
- 序列检测器，采用有限状态机实现，检测特定序列“101011”- Sequence detector, finite state machine, detection of a specific sequence 101011
FSM
- 序列检测器，采用移位寄存器实现，检测特定序列“101011”-Sequence detector using a shift register implementation, detection of a specific sequence 101011
77
- 基础实验_12_有限状态机 ：Moore型序列检测器-Basic experiment _12_ finite state machine: Moore type sequence detector
fsm
- verilog语言，有限状态机实现的序列检测器-verilog language, finite state machine sequence detector