资源列表
adder_ahead8bit
- 本文件提供了用verilog HDL语言实现的8位超前进位加法器,充分说明了超前进位加法器和普通加法器之间的区别.-using verilog HDL achieve the eight-ahead adder, fully demonstrates the CLA for ordinary Adder and the distinction between.
ug_fifo
- 可综合的FIFO存储器，全部在一个压缩包中，测试过，可以使用．-be integrated FIFO memory, all in a compressed package, tested, can be used.
CRC-Verilog
- 此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16-this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY
verilog_multiplier
- verilog实现16*16位乘法器，带测试文件-verilog achieve 16 * 16 multiplier, with test documents
100_jishuqi
- 该代码是100进制可逆计数器的源代码，已经在软件上调试过了，比较有用的-100 of the code is 229 CNTR the source code, the software has increased tried, the more useful
UART_ise7_bak
- 用FPGA 实现全双工异步串口（UART），与PC 机通信。1 位起始位；8 位数据位；一个停止位；无校验位；波特率为2400、4800、9600、11520 任选或可变（可用按键控制波特率模式）。-using FPGA full-duplex asynchronous serial port (UART), and PC communication. An initiation; 8 data spaces; One-stop; No Parity; Baud Rate for 2400,48
rs_decoder_31_19_6.tar
- Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
leon2-1[1].0.2a
- leon微处理器源代码，航空专用，功能强劲。包括详细说明-leon microprocessor source code, air flow, a strong function. Include a detailed descr iption of
8b10b_Encoder
- 应用VHDL设计的8b10b 编码器，对串行数据的高速传输有用。-application VHDL design 8b10b encoding device to the high-speed serial data transmission useful.
EXPT10_1_SONGER
- 乐曲硬件演奏电路设计,采用VHDL语言，quartus2开发平台-music concert circuit hardware design using VHDL, quartus2 Development Platform
KPCSMII
- Xillinx 的8位MCU软核的源代码，可在VertexII上运行，对CPU设计人员有很*意义-Xillinx the eight MCU soft-core source code can be run in VertexII. CPU designers to have great reference value
lf_decode
- 检测BT.656视频格式中内含的同步信号，可分离出行场同步信号。-detection R BT.656 video format containing the synchronization signal separable travel market synchronous signal.