资源列表
IIR-digital-filter-design-FPGA
- 基于FPGA的IIR低通数字滤波器设计 IIR low-pass digital filter design based on FPGA-IIR low-pass digital filter design based on FPGA
RGB-to-yuv422
- verilog语言写的视频数据处理相关的代码。实现功能为将RGB数据转化为BT656数据。-verilog language to write video data processing related to the code. Functions for the RGB data into the BT656 data.
v-watch
- 基于fpga的数字电压表的设计，包括ad转换，bcd码转换，分频，3选1模块，小数点生成模块，显示模块组成。-Based on the FPGA digital voltage meter design, including AD conversion, BCD code conversion, frequency,3 choose1module, a decimal point generating module, display module.
an-8-bit-left-shift-register
- 使用VHDL语言设计一个8 位左移移位寄存器。并给出了仿真波形。-Using VHDL to design an 8-bit left shift register. And simulation waveforms.
dac
- 基于fpga的数模转换器接口设计，转换数码管上显示的数字电压-Convert the digital voltage is displayed on the digital tube based the fpga DAC interface design,
oob_control
- sata协议物理层的OOB带外信号控制实现的VHDL代码-the sata protocol physical layer OOB band signal control VHDL code
anolog_conversion.rar
- analog to digital data conversion using vhdl,analog to digital data conversion using vhdl
uart_receive5bytes
- C语言实现CPLD串口接受五个字节，有校验，检验无效不做处理，接续检测接受，注释详细。-C language CPLD five byte serial accept check, test invalid without processing, splice detection to accept detailed notes.
LMS
- 用verilog编写的lms算法。可实现自适应滤波功能-Lms algorithm written in verilog. Adaptive filtering can be achieved
TEST
- Xilinx ///Microblaze中添加手动LCDIP的测试程序-Xilinx///Microblaze to add manually LCDIP test program
vrom
- 任天堂nes系统，存储器部分代码，希望大家用得着-Nintendo nes system, the memory part of the code, I hope you need it
ADD_SUB
- floating point fused add-subtract unit