资源列表
my_emac
- modelsim仿真网口MAC收发数据包的实现代码-Modelsim simulation port MAC transceiver packet implementation code
usb_ctrl
- USB2.0 控制接口代码，可用于与上位机进行通信传输。-USB2.0 interface controller，can be used for communication between host(computer) and FPGA board.
usbf_crc5
- 适用于刚入门FPGA 的人使用，简单的FPGA程序例程-Applies to people who are just touching FPGAs
CNN
- 最简单的R3信道编解码，包含有测试程序，非常实用-The simplest R3 channel codec contains a test program that is very useful
song
- 用硬件描述语言verilog hdl写的借助外设蜂鸣器实现产生固定的音乐。-Using Hardware Descr iption Language Verilog HDL written with peripheral buzzer to achieve fixed music.
I2C
- 自己编写的针对I2C芯片的Verilog读写程序，非常有用(I have written for I2C chip Verilog read and write procedures, very useful)
digital_clock
- vivado 学习资料 数字时钟设计 新建工程后导入相关文件（source）(digital clock Vivado learning materials Digital clock design, new construction, import related documents (source))
hua
- 使用verilog编写的AD7810控制器，经过了仿真验证(The AD7810 controller written by Verilog has been verified by simulation)
jtag fsm
- jtag接口的状态机实现，李庆华《通信IC设计》随机代码(State machine implementation of JTAG interface)
FIFO_ASY
- 异步FIFO，利用格雷码作异步FIFO指针减少亚稳态产生，利用同步寄存器放置亚稳态的级联传播。(Asynchronous FIFO, using gray code for asynchronous FIFO pointer to reduce metastable, cascade propagation using synchronous register placed metastable.)
encoder
- 基于1553B 模块 decoder 程序(decode_1553b_model.v)
FIFO
- 用verilog语言的实现FIFO存储器，以先进先出的方式处理数据(The FIFO memory is implemented in Verilog language, and data is processed in FIFO)