资源列表
shujuchuli
- FPGA处理AD转换数据,程序简单实用,带注释标注(FPGA processing AD conversion data, the program is simple and practical)
seq
- 实现序列检测功能,新手编程,已经在modelsim里检验过了功能完整,内附模块化testbench(Sequence detection function, novice programming)
day1
- 《四则运算小计算器设计过程实录》day1(verilog HDL code for day1,7 .rar documents in total.For more code u can put ur eye on my account.)
full_license
- quartus9.0 全功能license(quartus9.0 full license)
c_crc16
- CRC 16 development code
Digital_Clock
- 用verilog写的数字时钟代码,亲测可用,可自行编写test bench进行仿真(Written in Verilog digital clock code, pro test available, you can write your own test bench for simulation)
fenpin
- 实现奇数、偶数分频,fpga,Verilog,时钟分频(clock divider,frequency division)
asyn_fifo_204b_28
- 通用性异步fifo,性能非常好,推荐给大家(unverisal asyn fifo)
crc32_parallel
- CRC 32bit parallel generator
cdce_72010
- cdce72010 verilog code
IIC_Host
- 用VerilogHDL语言编写的I2C配置程序(VerilogHDL I2C source code)
4NandFlash
- 控制器顶层,以及实现功能模块简单的snandflash_top_ctrler(Simple nand_flash_top_ctrler)
