资源列表
AD5683 Driver
- AD5683 16位高精度DAC的FPGA程序，采用Verilog语言编写(AD5683 16 bit high precision DAC FPGA program, written in Verilog language)
zutil.h
- for everybody to understsn the file
crc_nguyenquanicd
- design crc module in data network transmission
D_cache
- 数据缓存的模块设计，连接流水线mem模块。(The module of data cache is designed to connect the pipeline MEM module.)
COUNT
- 本程序是基于verilog语言的程序，作用是计数器，数码管显示.(This procedure is based on Verilog language program, the role is to eliminate keyboard shaking, digital display.)
vhdl
- 用VHDL语言实现CD4527（BCD比例乘法器）仿真(The simulation of CD4527(BCD proportional multiplier))
8815397fft
- 基于MATLAB/FPGA的fft的verilog实现。(Verilog implementation of FFT based on MATLAB/FPGA)
C51
- 基于5-1单片机环境噪声测量仪的设计，包含主程序、中断服务程序、显示程序、(Based on 51 single-chip environmental noise detector proteus simulation file containing a set of project files noise.dsn Keil main code main.c 6 relevant articles and graduation thesis design through simulation)
mux16
- 基于quartus的FPGA乘法器Verilog程序(FPGA multiplier program based on quartus)
UC1676C
- 51单片机测试程序，ＩＣ:UC1676,4线串口(51 MCU test program, IC:UC1676 4-LINE, SPI INTERFACE)
apb_uart
- 这里是apb总线设计代码。这个源程序是基于verilog语言设计的(Here is the APB bus design code. This source program is designed based on Verilog language)
Verilog HDL
- 2015年全国电子设计大赛F题，时间间隔测量模块，占空比测量模块，ISE编写的verilog程序。(2015 national electronic design competition F title, time interval measurement module, verilog program written by ISE.)