资源列表
DDS.rar
- DDS信号发生器，利用VHDL实现，可根据频率控制字的改变输出不同频率的信号，最高可到达10MBPS,DDS signal generator, the use of VHDL realization of frequency control word in accordance with changes in output signals of different frequencies, the maximum arrival 10MBPS
DDS.rar
- 自己在Quartus下用VHDL编写的一个DDS程序。包括寄存器，累加器，波形存储器,In Quartus using VHDL procedures for the preparation of a DDS. Including the register, accumulator, waveform memory
sim.rar
- 通用的循环码编码器和（7,4）循环码译码器。采用VERILOG HDL编写，通过硬件验证。需使用modelsim 5.6仿真,Common cyclic code encoder and (7,4) cyclic code decoder. VERILOG HDL preparation used by the hardware verification. Need to use simulation modelsim 5.6
EP2C20_TEST.rar
- 内含无刷电机驱动VHDL模块，读码盘4倍频模块，并用NIOS核实现简单无刷电机闭环控制。,Brushless motor driver includes VHDL modules, reading frequency module plate 4, and nuclear NIOS simple closed-loop control of brushless motor.
scramble.rar
- 通信用加扰码VHDL电路，解决光传输过程中的连零和连一码的出现。,Communication scrambling circuit VHDL Code
Verilog_code_for_AWGN.rar
- verilog实现awgn信道噪声的代码，支持可变的信噪比。利用移位寄存器来实现伪随机序列。,verilog code for implementation of awgn channel noise. support variable snr. use LSFR to implement the pseudo random sequence.
fir_hdl.rar
- 一个 FIR 滤波器的 verilog 实现， 与 matlab 产生的 reference code 相互验证。,Verilog a FIR filter to achieve, with the reference code generated by matlab mutual authentication.
uart.zip
- uart串口通信程序，用状态机实现的；测试通过，并且实践过,uart
altera_up_avalon_sd_card_inter
- 基于VHDL的SD卡IP核，Altera公司推出的大学计划！最新版本9.0,VHDL-based IP core of the SD card, Altera' s university program launched! The latest version 9.0
uart_niosII.rar
- 基于FPGA芯片，在Nios II IDE软件的开发环境下写的NIos II 软核uart源代码！,Based on FPGA chip, the Nios II IDE software development environment written in NIos II soft-core uart source code!
trunk-hdlc.rar
- 高级链路层协议的实现，vhdl，fpga,- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern
Manchester.rar
- 曼彻斯特编解码源代码,还包含曼彻斯特码的说明文档,Manchester Encoder-Decoder