资源列表
dxp_intlib_by_myself
- 该软件包为dxp的集成元件库，本人整理的。方便大家使用-The integrated software package for the dxp library, I finishing. Convenience we use
LAB17
- 学校FPGA实验教学work1之十七讲，西欧啊次哦十六讲-Schools Experiment work1 the seventh FPGA say, oh sixteen times in Western Europe say ah
new_RS_Verilog
- 这是基于FPGA的RS编解码的实际例子。我已经调试完成！- This is arranges the decoding based on FPGA RS the actual example. I already debugged complete!
count
- 吉大短学期CPLD实习程序 可逆10 进制计数器，用1 位拨码开关进行加减控制：输入为0 时进行加计数，当输入为1 时进行减计数；用1 位拨码开关进行同步清零控制：输入为0 时清零，输入为1时正常计数。计数结果用数码管显示-Chittagong short term internship program CPLD reversible binary counter 10, with an addition and subtraction DIP switch control: when th
motor-positioning-control-vhdl
- 步进电机定位控制系统VHDL程序与仿真,绝对能用,经本人毕设测试!-Stepper motor positioning control system and simulation of VHDL program, absolutely can, after I completed the test set!
fir_lms
- verilog语言编写LMS（最小均方误差）自适应滤波器。-verilog language LMS (least mean square error) adaptive filter.
sqrt_Verilog
- Verilog实现开平方模块，内含有具体的算法描述Word文档，简单清晰明了。-sqrt with Verilog HDL. It is useful.
aes-core
- Verilog编写的美国标准加密算法AES的硬件实现包含完整代码及测试程序。- Verilog the compilation American standard encryption algorithm AES hardware realizes contains the complete code and the test order.
CY7c68013
- CY7c68013的读写程序,开发环境是ISE-CY7c68013 write and read program
chengfaqi
- 基于FPGA采用时序逻辑方法设计的16位乘法器代码-FPGA-based temporal logic designed using 16-bit multiplier code
Verilog_pingpang
- 其实乒乓操作用面积换速度，本文件是用verilog实现乒乓操作-In fact, with an area for ping-pong operation speed, this document is to achieve pong operation verilog
Adaptive-echo-cancellation
- 自适应回波消除，FPGA方面的设计论文，对大家有用的可以下下来-Adaptive echo cancellation, FPGA design aspects of paper, can be useful to all of us look down under