资源列表
FIFOED_UART
- CAL_UART核verilog源码，带FIFO，FIFO深度可设置。-fifoed uart ip core. cal_uart.
CRC-8
- VHDL code for CRC-8 computing using 32 bit input (parallel)
yuanchengxu
- 基于Verilog HDL的通信系统设计-Design of communication system based on Verilog HDL
rt_32bit
- 通过Verilog实现的基于FPGA实现429总线格式转换接收程序-FPGA code for receive 429 message
digital_voltage
- VHDL开发的数字电压表，量程5V，精度0.01V，在Sparten3E FPGA运行通过-VHDL development of digital voltmeter, range 5V, precision 0.01V, running through the Sparten3E FPGA
LectureNote
- 高级Xilinx FPGA ISE设计教程，详细讲解优化Xilinx设计结构改善时序，减少implementation时间，减少调试时间，片上验证以及调试等FPGA设计深入环节，是深入理解FPGA设计的不可多得的好书。-Advanced Xilinx FPGA ISE design tutorial, explain in detail the structure of the Xilinx design optimization to improve timing, reduce implem
61i_sqrrt_cordic_v2_0_vhdl_ise
- SQRT+ Cordic ISE Xilinx
LKB001-U1-LK650-06
- 16通道高速DI数据采集模块程序，采用verilog 编写，quartus，cyclone EP1C3T1-high LVDS comm DI module hollysys bei jing quartus verilog
simple_fm_receiver_latest.tar
- 用FPGA实现简单的FM接收机，d/a模块用扬声器-FPGA implementation using a simple FM receiver, d/a module with speaker
VHDL-source-code
- 一些有用的VHDL代码 包括伪随机序列发生器等-VHDL code, including some useful pseudo-random sequence generator, etc.
test5
- 用VHDL设计8位算术逻辑运算器，并将运算结果显示通过俩个七段数码管显示-Design with VHDL 8-bit arithmetic and logic devices, and computing results show that by two seven-segment LED display
Code
- 用于数字积分器的设计，主要涉及VHDL、Verilog等FPGA编程语言。-Design of Digital Integrator