资源列表
ISA
- ISA总线接口，采用verilog HDL语言编写，值得参考！-ISA bus interface, using verilog HDL language, worthy of reference.
ML_506_3_lcd_1602
- lcd1602的四线控制的verilog源码，在ML506平台上已经通过验证-The lcd1602 four-line control of Verilog source code which has been verified on the ML506 platform.
AIC23_Configure_Test
- 用verilog写的关于AIC23的配置程序，在板子上已经验证通过。-Verilog to write about AIC23 configuration program, the board has been verified.
AMSD_in_GUI.tar
- 锁相环（pll）AMS仿真实例，平台为cadence+ius。-tutorial for the simulation of mixed signal pll
xapp1014-xilinx-sdi
- 用fpga实现SDI，每一步都很清楚 搞视频的可以参考-Fpga realization of SDI, each step are clearly engaged in the video can refer to
mult_16
- 用verilog实现对三个16位数进行相加乘法器-Three 16-digit sum of the multiplier Verilog
pinlvji
- 使用verilog语言设计一个3位十进制数字式频率计，其测量范围为1MHz，量程为10kMz,100kMz和1MMz三档（最大读数分别为：9.99kMz，99.9kMz和999kMz）-Use verilog language, design a three decimal digital frequency meter
traffic
- 红绿交通灯。哈工大计算机学院数字逻辑大作业，０９籍～～～可以直接用的哈-Red and green traffic lights. Harbin Institute of Computer Science, the digital logic operations, 09 Ji ~ ~ ~ can be used directly
FFT1024
- FPGA的1024点的FFT算法程序，经过调试，程序移植性强。-1024-point FFT algorithm in the FPGA program, debugging, program portability.
frame-synchronous-search-circuit
- 用verilog语言编写的帧同步搜索电路，输入数据data为8 bit并行数据流，基本结构为数据帧，帧长为10字节，帧同步字为H“FF”。clk为输入同步时钟。-Verilog language for frame synchronous search circuit, the input data is data for the 8-bit parallel data stream, the basic structure of the data frame, the frame lengt
Waveform-generator(DAC902)
- 信号发生器可1Hz - 10MHz 可调频调幅产生ASKPSK-Waveform generator(DAC902)
time
- fpga万年历 vhdl语言 能实现现实时分秒年月日 及闰年判断 整点报时-every second when the fpga calendar VHDL language can achieve real date and leap year to judge the whole point of time