资源列表
pip
- 好用的视频处理verilog源代码，主要功能是实现picture in picture。-Easy to use video processing verilog source code, the main function is to achieve the picture in. picture.
yuv2rgb
- 大公司解禁的yuv2rgb的转换的verilog源代码，供大家学习。-Large companies lifted yuv2rgb the conversion of the verilog source code for everyone to learn.
AM
- FPGA简单实现幅度调制，所使用软件为ISE，仿真工具是modelsim-FPGA realization of a simple amplitude modulation, the use of software for the ISE, and simulation tools is modelsim
cfq
- 基于fpga的乘法器设计，完整代码及工程-Fpga-based multiplier design, the complete code and engineering
prbs
- 高速并行数据伪随机化模块，包括发送侧的随机化和接收侧的去随机化，以及测试模块-High-speed parallel pseudo-random data modules, including randomized and receive side of sending side to randomization, and the test module
m_seq
- 用VHDL代码编写的m序列发生器，包含发生器和测试用例模块-M sequence generator written in VHDL code, including the generator and the test case module
qpsk
- 用ISE10.1 实现的简单qpsk功能实验-qpsk lab achviment
FPGA_control_ADF7021
- 用FPGA控制射频芯片ADF7021的Verilog程序-Verilog program the FPGA to control the RF chip ADF7021
IIs_interface_v4
- IIs接口的Verilog程序，此接口用于传输语音数据，程序好用-IIs interface Verilog programs, this interface is used to transmit voice and data, easy to use program
Multiplier16
- 本文设计了一种可以实现16位有符号/无符号二进制数乘法的乘法器。该乘法器采用了补码一位乘（Booth算法), 简化了部分积的数目, 减少了某些加法运算,从而提高了运算速度。该乘法器利用Verilog代码实现，通过Modelsim软件对相应的波形进行仿真验证，并通过QuartusII软件对源码进行编译综合。-This paper designed a 16 signed/unsigned binary number multiplication of the multiplier can be a
mult_16
- 这是自己设计的16位乘法器设计，其中用了booth编码，，4-2压缩器等，-This is a 16 multiplier design of their own design, including the booth encoding 4-2 compression, etc.,
EtherCAT_IPCore_Xilinl
- EtherCAT从站控制器芯片ET1817及其IP_Core应用-EtherCAT Slave Controller IP Core for Xilinx FPGAs